Searched refs:vqsub (Results 1 - 23 of 23) sorted by relevance

/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dneon-sub-encoding.s65 @ CHECK: vqsub.s8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf2]
66 vqsub.s8 d16, d16, d17
67 @ CHECK: vqsub.s16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf2]
68 vqsub.s16 d16, d16, d17
69 @ CHECK: vqsub.s32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf2]
70 vqsub.s32 d16, d16, d17
71 @ CHECK: vqsub.s64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf2]
72 vqsub.s64 d16, d16, d17
73 @ CHECK: vqsub.u8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf3]
74 vqsub
[all...]
/external/llvm/test/MC/ARM/
H A Dneon-sub-encoding.s91 @ CHECK: vqsub.s8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf2]
92 vqsub.s8 d16, d16, d17
93 @ CHECK: vqsub.s16 d16, d16, d17 @ encoding: [0xb1,0x02,0x50,0xf2]
94 vqsub.s16 d16, d16, d17
95 @ CHECK: vqsub.s32 d16, d16, d17 @ encoding: [0xb1,0x02,0x60,0xf2]
96 vqsub.s32 d16, d16, d17
97 @ CHECK: vqsub.s64 d16, d16, d17 @ encoding: [0xb1,0x02,0x70,0xf2]
98 vqsub.s64 d16, d16, d17
99 @ CHECK: vqsub.u8 d16, d16, d17 @ encoding: [0xb1,0x02,0x40,0xf3]
100 vqsub
[all...]
/external/capstone/suite/MC/ARM/
H A Dneon-sub-encoding.s.cs43 0xb1,0x02,0x40,0xf2 = vqsub.s8 d16, d16, d17
44 0xb1,0x02,0x50,0xf2 = vqsub.s16 d16, d16, d17
45 0xb1,0x02,0x60,0xf2 = vqsub.s32 d16, d16, d17
46 0xb1,0x02,0x70,0xf2 = vqsub.s64 d16, d16, d17
47 0xb1,0x02,0x40,0xf3 = vqsub.u8 d16, d16, d17
48 0xb1,0x02,0x50,0xf3 = vqsub.u16 d16, d16, d17
49 0xb1,0x02,0x60,0xf3 = vqsub.u32 d16, d16, d17
50 0xb1,0x02,0x70,0xf3 = vqsub.u64 d16, d16, d17
51 0xf2,0x02,0x40,0xf2 = vqsub.s8 q8, q8, q9
52 0xf2,0x02,0x50,0xf2 = vqsub
[all...]
/external/arm-neon-tests/
H A DAndroid.mk25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
H A DMakefile40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
H A Dref_vqsub.c26 #define INSN_NAME vqsub
/external/libhevc/common/arm/
H A Dihevc_deblk_luma_horz.s202 vqsub.u8 d31,d26,d1
217 vqsub.u8 d17,d27,d1
238 vqsub.u8 d31,d28,d1
283 vqsub.u8 d31,d25,d1
291 vqsub.u8 d17,d24,d1
379 vqsub.u8 d31,d23,d1
H A Dihevc_deblk_luma_vert.s201 vqsub.u8 d30,d7,d19
241 vqsub.u8 d31,d5,d19
252 vqsub.u8 d25,d4,d19
278 vqsub.u8 d31,d2,d19
289 vqsub.u8 d28,d3,d19
301 vqsub.u8 d31,d6,d19
/external/libavc/common/arm/
H A Dih264_deblk_chroma_a9.s317 vqsub.u8 q2, q2, q7 @Q2 = p0 - delta
319 vqsub.u8 q0, q0, q7 @Q0 = q0 - delta
445 vqsub.u8 q12, q1, q7 @p0-|delta|
446 vqsub.u8 q13, q2, q7 @q0-|delta|
641 vqsub.u8 d12, d1, d7 @p0-|delta|
642 vqsub.u8 d13, d2, d7 @q0-|delta|
959 vqsub.u8 q2, q2, q7 @Q2 = p0 - delta
961 vqsub.u8 q0, q0, q7 @Q0 = q0 - delta
1099 vqsub.u8 q12, q1, q7 @p0-|delta|
1100 vqsub
[all...]
H A Dih264_deblk_luma_a9.s170 vqsub.u8 q3, q3, q9 @Q3 = p0 - delta
174 vqsub.u8 q0, q0, q9 @Q0 = q0 - delta
524 vqsub.u8 q11, q3, q15 @clip(p0-delta)
530 vqsub.u8 q4, q4, q15 @clip(q0-delta)
1065 vqsub.u8 d11, d3, d15 @clip(p0-delta)
1068 vqsub.u8 d4, d4, d15 @clip(q0-delta)
/external/libvpx/libvpx/vpx_dsp/arm/
H A Dloopfilter_8_neon.asm322 vqsub.s8 d29, d25, d26 ; filter = clamp(ps1-qs1)
343 vqsub.s8 d21, d21, d29 ; oq0 = clamp(qs0 - filter1)
350 vqsub.s8 d26, d26, d29 ; oq1 = clamp(qs1 - filter)
H A Dloopfilter_neon.c415 filter = vqsub##r##s8(ps1, qs1); \
417 t = vqsub##r##s8(qs0, ps0); \
431 qs0 = vqsub##r##s8(qs0, filter1); \
440 qs1 = vqsub##r##s8(qs1, filter); \
H A Dloopfilter_16_neon.asm467 vqsub.s8 d29, d25, d26 ; filter = clamp(ps1-qs1)
485 vqsub.s8 d23, d23, d29 ; oq0 = clamp(qs0 - filter1)
492 vqsub.s8 d26, d26, d29 ; oq1 = clamp(qs1 - filter)
/external/valgrind/none/tests/arm/
H A Dneon128.stdout.exp267 vqsub.s32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
268 vqsub.s32 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
269 vqsub.s32 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
270 vqsub.s32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
271 vqsub.s32 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
272 vqsub.s32 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
273 vqsub.s16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
274 vqsub.s16 q0, q1, q2 :: Qd 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
275 vqsub.s16 q0, q1, q2 :: Qd 0x151d18a5 0x141c1ea4 0x131b19a3 0x121f1da7 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
276 vqsub
[all...]
H A Dneon64.stdout.exp361 vqsub.s32 d0, d1, d2 :: Qd 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
362 vqsub.s32 d0, d1, d2 :: Qd 0x0706048c 0x03020088 Qm (i32)0x00000018 Qn (i32)0x00000078 fpscr: 00000000
363 vqsub.s32 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
364 vqsub.s32 d0, d1, d2 :: Qd 0x0706048c 0x03020088 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
365 vqsub.s16 d0, d1, d2 :: Qd 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
366 vqsub.s16 d0, d1, d2 :: Qd 0x0706048c 0x03020088 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
367 vqsub.s8 d0, d1, d2 :: Qd 0x00000080 0x00000080 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 08000000
368 vqsub.s8 d0, d1, d2 :: Qd 0x0706058c 0x03020188 Qm (i32)0x0000008c Qn (i32)0x00000078 fpscr: 00000000
369 vqsub.s8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002 fpscr: 00000000
370 vqsub
[all...]
/external/v8/src/compiler/arm/
H A Dcode-generator-arm.cc1712 __ vqsub(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
1765 __ vqsub(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
1834 __ vqsub(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
1886 __ vqsub(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h5434 void vqsub(
5436 void vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
5437 vqsub(al, dt, rd, rn, rm);
5440 void vqsub(
5442 void vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
5443 vqsub(al, dt, rd, rn, rm);
H A Ddisasm-aarch32.h2283 void vqsub(
2286 void vqsub(
H A Dassembler-aarch32.cc23728 void Assembler::vqsub( function in class:vixl::aarch32::Assembler
23755 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
23758 void Assembler::vqsub( function in class:vixl::aarch32::Assembler
23785 Delegate(kVqsub, &Assembler::vqsub, cond, dt, rd, rn, rm);
H A Dmacro-assembler-aarch32.h8990 vqsub(cond, dt, rd, rn, rm);
9005 vqsub(cond, dt, rd, rn, rm);
H A Ddisasm-aarch32.cc6011 void Disassembler::vqsub( function in class:vixl::aarch32::Disassembler
6022 void Disassembler::vqsub( function in class:vixl::aarch32::Disassembler
[all...]
/external/v8/src/arm/
H A Dassembler-arm.h1376 void vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
H A Dassembler-arm.cc4393 void Assembler::vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, function in class:v8::internal::Assembler
4396 // Qd = vqsub(Qn, Qm) SIMD integer saturating subtraction.

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