Searched refs:zip1 (Results 1 - 23 of 23) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-perm.s41 zip1 v0.8b, v1.8b, v2.8b
42 zip1 v0.16b, v1.16b, v2.16b
43 zip1 v0.4h, v1.4h, v2.4h
44 zip1 v0.8h, v1.8h, v2.8h
45 zip1 v0.2s, v1.2s, v2.2s
46 zip1 v0.4s, v1.4s, v2.4s
47 zip1 v0.2d, v1.2d, v2.2d
49 // CHECK: zip1 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x38,0x02,0x0e]
50 // CHECK: zip1 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x38,0x02,0x4e]
51 // CHECK: zip1 v
[all...]
H A Dneon-diagnostics.s6528 zip1 v0.16b, v1.8b, v2.8b
6529 zip1 v0.8b, v1.4b, v2.4b
6530 zip1 v0.8h, v1.4h, v2.4h
6531 zip1 v0.4h, v1.2h, v2.2h
6532 zip1 v0.4s, v1.2s, v2.2s
6533 zip1 v0.2s, v1.1s, v2.1s
6534 zip1 v0.2d, v1.1d, v2.1d
6535 zip1 v0.1d, v1.1d, v2.1d
6538 // CHECK-ERROR: zip1 v0.16b, v1.8b, v2.8b
6541 // CHECK-ERROR: zip1 v
[all...]
/external/capstone/suite/MC/AArch64/
H A Dneon-perm.s.cs16 0x20,0x38,0x02,0x0e = zip1 v0.8b, v1.8b, v2.8b
17 0x20,0x38,0x02,0x4e = zip1 v0.16b, v1.16b, v2.16b
18 0x20,0x38,0x42,0x0e = zip1 v0.4h, v1.4h, v2.4h
19 0x20,0x38,0x42,0x4e = zip1 v0.8h, v1.8h, v2.8h
20 0x20,0x38,0x82,0x0e = zip1 v0.2s, v1.2s, v2.2s
21 0x20,0x38,0x82,0x4e = zip1 v0.4s, v1.4s, v2.4s
22 0x20,0x38,0xc2,0x4e = zip1 v0.2d, v1.2d, v2.2d
/external/libhevc/decoder/arm64/
H A Dihevcd_itrans_recon_dc_chroma.s205 zip1 v2.8b, v31.8b, v3.8b
206 zip1 v4.8b, v29.8b, v5.8b
207 zip1 v6.8b, v27.8b, v7.8b
208 zip1 v8.8b, v25.8b, v9.8b
/external/libhevc/common/arm64/
H A Dihevc_intra_pred_chroma_mode2.s272 zip1 v0.8b, v0.8b, v1.8b
281 zip1 v2.8b, v2.8b, v3.8b
291 zip1 v4.8b, v4.8b, v5.8b
298 zip1 v6.8b, v6.8b, v7.8b
H A Dihevc_deblk_chroma_horz.s149 zip1 v4.8h, v30.8h, v31.8h
152 zip1 v18.8h, v28.8h, v29.8h
H A Dihevc_inter_pred_filters_luma_horz.s516 zip1 v0.2s, v20.2s, v22.2s
518 zip1 v1.2s, v21.2s, v23.2s
526 zip1 v2.2s, v20.2s, v22.2s
528 zip1 v3.2s, v21.2s, v23.2s
536 zip1 v4.2s, v20.2s, v22.2s
538 zip1 v5.2s, v21.2s, v23.2s
546 zip1 v6.2s, v20.2s, v22.2s
548 zip1 v7.2s, v21.2s, v23.2s
H A Dihevc_inter_pred_luma_horz_w16out.s216 zip1 v0.2s, v20.2s, v22.2s
218 zip1 v1.2s, v21.2s, v23.2s
226 zip1 v2.2s, v20.2s, v22.2s
228 zip1 v3.2s, v21.2s, v23.2s
236 zip1 v4.2s, v20.2s, v22.2s
238 zip1 v5.2s, v21.2s, v23.2s
271 zip1 v6.2s, v20.2s, v22.2s
273 zip1 v7.2s, v21.2s, v23.2s
H A Dihevc_intra_pred_chroma_planar.s174 zip1 v29.8b, v17.8b, v25.8b
328 zip1 v29.8b, v17.8b, v25.8b
342 zip1 v29.8b, v17.8b, v25.8b
H A Dihevc_inter_pred_chroma_horz.s734 zip1 v0.2s, v20.2s, v16.2s
736 zip1 v1.2s, v21.2s, v17.2s
738 zip1 v2.2s, v22.2s, v18.2s
740 zip1 v3.2s, v23.2s, v19.2s
H A Dihevc_inter_pred_chroma_horz_w16out.s706 //zip1 v0.2s, v0.2s, v12.2s
708 //zip1 v2.2s, v2.2s, v14.2s
710 //zip1 v4.2s, v4.2s, v16.2s
712 //zip1 v6.2s, v6.2s, v18.2s
716 zip1 v0.2s, v20.2s, v16.2s
718 zip1 v1.2s, v21.2s, v17.2s
720 zip1 v2.2s, v22.2s, v18.2s
722 zip1 v3.2s, v23.2s, v19.2s
/external/python/cpython3/Lib/test/
H A Dtest_zipimport.py265 zip1 = os.path.abspath("path1.zip")
266 self.makeZip(files1, zip1)
271 # zip2 should override zip1.
272 sys.path.insert(0, zip1)
286 # Its __path__ is an iterable of 1 element from zip1.
319 # Finally subpkg.TESTMOD + '3' only exists in zip1.
336 zip1 = os.path.abspath("path1.zip")
337 self.makeZip(files1, zip1)
347 # zip2 should override zip1.
348 sys.path.insert(0, zip1)
[all...]
/external/libavc/common/armv8/
H A Dih264_intra_pred_chroma_av8.s478 zip1 v5.8h, v4.8h, v24.8h
481 zip1 v7.8h, v6.8h, v26.8h
484 zip1 v1.8h, v0.8h, v2.8h
495 zip1 v9.8h, v8.8h, v10.8h
H A Dih264_deblk_chroma_av8.s527 zip1 v31.8b, v12.8b, v13.8b
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2496 __ zip1(v22.V16B(), v9.V16B(), v6.V16B());
2497 __ zip1(v23.V2D(), v11.V2D(), v2.V2D());
2498 __ zip1(v26.V2S(), v16.V2S(), v9.V2S());
2499 __ zip1(v1.V4H(), v9.V4H(), v7.V4H());
2500 __ zip1(v0.V4S(), v30.V4S(), v20.V4S());
2501 __ zip1(v30.V8B(), v17.V8B(), v15.V8B());
2502 __ zip1(v17.V8H(), v8.V8H(), v2.V8H());
H A Dtest-simulator-aarch64.cc4421 DEFINE_TEST_NEON_3SAME(zip1, Basic)
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2242 void zip1(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-aarch64.h2284 V(zip1, Zip1) \
H A Dsimulator-aarch64.h2516 LogicVRegister zip1(VectorFormat vform,
H A Dsimulator-aarch64.cc5162 zip1(vf, rd, rn, rm);
H A Dassembler-aarch64.cc3537 void Assembler::zip1(const VRegister& vd,
H A Dlogic-aarch64.cc3493 LogicVRegister Simulator::zip1(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp[all...]

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