Searched refs:zip2 (Results 1 - 23 of 23) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-perm.s89 zip2 v0.8b, v1.8b, v2.8b
90 zip2 v0.16b, v1.16b, v2.16b
91 zip2 v0.4h, v1.4h, v2.4h
92 zip2 v0.8h, v1.8h, v2.8h
93 zip2 v0.2s, v1.2s, v2.2s
94 zip2 v0.4s, v1.4s, v2.4s
95 zip2 v0.2d, v1.2d, v2.2d
97 // CHECK: zip2 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x78,0x02,0x0e]
98 // CHECK: zip2 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x78,0x02,0x4e]
99 // CHECK: zip2 v
[all...]
H A Dneon-diagnostics.s6562 zip2 v0.16b, v1.8b, v2.8b
6563 zip2 v0.8b, v1.4b, v2.4b
6564 zip2 v0.8h, v1.4h, v2.4h
6565 zip2 v0.4h, v1.2h, v2.2h
6566 zip2 v0.4s, v1.2s, v2.2s
6567 zip2 v0.2s, v1.1s, v2.1s
6568 zip2 v0.2d, v1.1d, v2.1d
6569 zip2 v0.1d, v1.1d, v2.1d
6572 // CHECK-ERROR: zip2 v0.16b, v1.8b, v2.8b
6575 // CHECK-ERROR: zip2 v
[all...]
/external/capstone/suite/MC/AArch64/
H A Dneon-perm.s.cs37 0x20,0x78,0x02,0x0e = zip2 v0.8b, v1.8b, v2.8b
38 0x20,0x78,0x02,0x4e = zip2 v0.16b, v1.16b, v2.16b
39 0x20,0x78,0x42,0x0e = zip2 v0.4h, v1.4h, v2.4h
40 0x20,0x78,0x42,0x4e = zip2 v0.8h, v1.8h, v2.8h
41 0x20,0x78,0x82,0x0e = zip2 v0.2s, v1.2s, v2.2s
42 0x20,0x78,0x82,0x4e = zip2 v0.4s, v1.4s, v2.4s
43 0x20,0x78,0xc2,0x4e = zip2 v0.2d, v1.2d, v2.2d
/external/libhevc/common/arm64/
H A Dihevc_intra_pred_chroma_mode2.s273 zip2 v1.8b, v0.8b, v1.8b
282 zip2 v3.8b, v2.8b, v3.8b
292 zip2 v5.8b, v4.8b, v5.8b
299 zip2 v7.8b, v6.8b, v7.8b
H A Dihevc_inter_pred_filters_luma_horz.s517 zip2 v12.2s, v20.2s, v22.2s //vector zip the i iteration and ii interation in single register
519 zip2 v13.2s, v21.2s, v23.2s
527 zip2 v14.2s, v20.2s, v22.2s
529 zip2 v15.2s, v21.2s, v23.2s
537 zip2 v16.2s, v20.2s, v22.2s
539 zip2 v17.2s, v21.2s, v23.2s
547 zip2 v18.2s, v20.2s, v22.2s
549 zip2 v19.2s, v21.2s, v23.2s
H A Dihevc_inter_pred_luma_horz_w16out.s217 zip2 v12.2s, v20.2s, v22.2s //vector zip the i iteration and ii interation in single register
219 zip2 v13.2s, v21.2s, v23.2s
227 zip2 v14.2s, v20.2s, v22.2s
229 zip2 v15.2s, v21.2s, v23.2s
237 zip2 v16.2s, v20.2s, v22.2s
239 zip2 v17.2s, v21.2s, v23.2s
272 zip2 v18.2s, v20.2s, v22.2s
274 zip2 v19.2s, v21.2s, v23.2s
H A Dihevc_intra_pred_chroma_planar.s175 zip2 v25.8b, v17.8b, v25.8b
329 zip2 v25.8b, v17.8b, v25.8b
343 zip2 v25.8b, v17.8b, v25.8b
H A Dihevc_inter_pred_chroma_horz.s735 zip2 v4.2s, v20.2s, v16.2s //vector zip the i iteration and ii interation in single register
737 zip2 v5.2s, v21.2s, v17.2s
739 zip2 v6.2s, v22.2s, v18.2s
741 zip2 v7.2s, v23.2s, v19.2s
H A Dihevc_inter_pred_chroma_horz_w16out.s707 //zip2 v12.2s, v0.2s, v12.2s //vector zip the i iteration and ii interation in single register
709 //zip2 v14.2s, v2.2s, v14.2s
711 //zip2 v16.2s, v4.2s, v16.2s
713 //zip2 v18.2s, v6.2s, v18.2s
717 zip2 v4.2s, v20.2s, v16.2s //vector zip the i iteration and ii interation in single register
719 zip2 v5.2s, v21.2s, v17.2s
721 zip2 v6.2s, v22.2s, v18.2s
723 zip2 v7.2s, v23.2s, v19.2s
/external/python/cpython3/Lib/test/
H A Dtest_zipimport.py268 zip2 = TEMP_DIR
269 self.makeTree(files2, zip2)
271 # zip2 should override zip1.
273 sys.path.insert(0, zip2)
309 # subpkg.TESTMOD exists in both zips should load from zip2.
314 # subpkg.TESTMOD + '2' only exists in zip2.
344 zip2 = os.path.abspath("path2.zip")
345 self.makeZip(files2, zip2)
347 # zip2 should override zip1.
349 sys.path.insert(0, zip2)
[all...]
H A Dtest_zipfile.py1614 self.zip2 = zipfile.ZipFile(TESTFN2, "r")
1619 self.zip2.close()
1626 self.assertRaises(RuntimeError, self.zip2.read, "zero")
1631 self.zip2.setpassword(b"perl")
1632 self.assertRaises(RuntimeError, self.zip2.read, "zero")
1638 self.zip2.setpassword(b"12345")
1639 self.assertEqual(self.zip2.read("zero"), self.plain2)
/external/libavc/common/armv8/
H A Dih264_intra_pred_chroma_av8.s479 zip2 v24.8h, v4.8h, v24.8h
482 zip2 v26.8h, v6.8h, v26.8h
485 zip2 v2.8h, v0.8h, v2.8h
496 zip2 v10.8h, v8.8h, v10.8h
H A Dih264_deblk_chroma_av8.s528 zip2 v13.8b, v12.8b, v13.8b
/external/python/cpython2/Lib/test/
H A Dtest_zipfile.py1328 self.zip2 = zipfile.ZipFile(TESTFN2, "r")
1333 self.zip2.close()
1340 self.assertRaises(RuntimeError, self.zip2.read, "zero")
1345 self.zip2.setpassword("perl")
1346 self.assertRaises(RuntimeError, self.zip2.read, "zero")
1352 self.zip2.setpassword("12345")
1353 self.assertEqual(self.zip2.read("zero"), self.plain2)
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2503 __ zip2(v23.V16B(), v10.V16B(), v11.V16B());
2504 __ zip2(v30.V2D(), v6.V2D(), v14.V2D());
2505 __ zip2(v9.V2S(), v10.V2S(), v21.V2S());
2506 __ zip2(v8.V4H(), v24.V4H(), v29.V4H());
2507 __ zip2(v0.V4S(), v21.V4S(), v23.V4S());
2508 __ zip2(v25.V8B(), v23.V8B(), v30.V8B());
2509 __ zip2(v7.V8H(), v10.V8H(), v30.V8H());
H A Dtest-simulator-aarch64.cc4424 DEFINE_TEST_NEON_3SAME(zip2, Basic)
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2245 void zip2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-aarch64.h2285 V(zip2, Zip2)
H A Dsimulator-aarch64.h2520 LogicVRegister zip2(VectorFormat vform,
H A Dsimulator-aarch64.cc5165 zip2(vf, rd, rn, rm);
H A Dassembler-aarch64.cc3544 void Assembler::zip2(const VRegister& vd,
H A Dlogic-aarch64.cc3513 LogicVRegister Simulator::zip2(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp[all...]

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