| /art/test/961-default-iface-resolution-gen/ |
| H A D | run | 18 ./default-run "$@" --dex2oat-timeout 120 --dex2oat-rt-timeout 180
|
| /art/runtime/ |
| H A D | reference_table_test.cc | 80 ReferenceTable rt("test", 0, 11);
85 rt.Dump(oss);
87 EXPECT_EQ(0U, rt.Size());
91 rt.Remove(nullptr);
92 EXPECT_EQ(0U, rt.Size());
95 rt.Remove(o1);
96 EXPECT_EQ(0U, rt.Size());
100 rt.Add(o1);
101 EXPECT_EQ(1U, rt.Size());
103 rt
[all...] |
| /art/compiler/utils/mips/ |
| H A D | assembler_mips.h | 299 void Addu(Register rd, Register rs, Register rt);
300 void Addiu(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label);
301 void Addiu(Register rt, Register rs, uint16_t imm16);
302 void Subu(Register rd, Register rs, Register rt);
304 void MultR2(Register rs, Register rt); // R2
305 void MultuR2(Register rs, Register rt); // R2
306 void DivR2(Register rs, Register rt); // R2
307 void DivuR2(Register rs, Register rt); // R2
308 void MulR2(Register rd, Register rs, Register rt); // R2
309 void DivR2(Register rd, Register rs, Register rt); // R
[all...] |
| H A D | assembler_mips.cc | 257 Register rt,
262 CHECK_NE(rt, kNoRegister);
266 static_cast<uint32_t>(rt) << kRtShift |
274 uint32_t MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument
276 CHECK_NE(rt, kNoRegister);
279 static_cast<uint32_t>(rt) << kRtShift |
454 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { argument
455 DsFsmInstr(EmitR(0, rs, rt, rd, 0, 0x21)).GprOuts(rd).GprIns(rs, rt);
458 void MipsAssembler::Addiu(Register rt, Registe argument
255 EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) argument
465 Addiu(Register rt, Register rs, uint16_t imm16) argument
469 Subu(Register rd, Register rs, Register rt) argument
473 MultR2(Register rs, Register rt) argument
478 MultuR2(Register rs, Register rt) argument
483 DivR2(Register rs, Register rt) argument
488 DivuR2(Register rs, Register rt) argument
493 MulR2(Register rd, Register rs, Register rt) argument
498 DivR2(Register rd, Register rs, Register rt) argument
504 ModR2(Register rd, Register rs, Register rt) argument
510 DivuR2(Register rd, Register rs, Register rt) argument
516 ModuR2(Register rd, Register rs, Register rt) argument
522 MulR6(Register rd, Register rs, Register rt) argument
527 MuhR6(Register rd, Register rs, Register rt) argument
532 MuhuR6(Register rd, Register rs, Register rt) argument
537 DivR6(Register rd, Register rs, Register rt) argument
542 ModR6(Register rd, Register rs, Register rt) argument
547 DivuR6(Register rd, Register rs, Register rt) argument
552 ModuR6(Register rd, Register rs, Register rt) argument
557 And(Register rd, Register rs, Register rt) argument
561 Andi(Register rt, Register rs, uint16_t imm16) argument
565 Or(Register rd, Register rs, Register rt) argument
569 Ori(Register rt, Register rs, uint16_t imm16) argument
573 Xor(Register rd, Register rs, Register rt) argument
577 Xori(Register rt, Register rs, uint16_t imm16) argument
581 Nor(Register rd, Register rs, Register rt) argument
585 Movz(Register rd, Register rs, Register rt) argument
590 Movn(Register rd, Register rs, Register rt) argument
595 Seleqz(Register rd, Register rs, Register rt) argument
600 Selnez(Register rd, Register rs, Register rt) argument
625 Seb(Register rd, Register rt) argument
629 Seh(Register rd, Register rt) argument
633 Wsbh(Register rd, Register rt) argument
637 Bitswap(Register rd, Register rt) argument
642 Sll(Register rd, Register rt, int shamt) argument
647 Srl(Register rd, Register rt, int shamt) argument
652 Rotr(Register rd, Register rt, int shamt) argument
657 Sra(Register rd, Register rt, int shamt) argument
662 Sllv(Register rd, Register rt, Register rs) argument
666 Srlv(Register rd, Register rt, Register rs) argument
670 Rotrv(Register rd, Register rt, Register rs) argument
674 Srav(Register rd, Register rt, Register rs) argument
678 Ext(Register rd, Register rt, int pos, int size) argument
686 Ins(Register rd, Register rt, int pos, int size) argument
694 Lsa(Register rd, Register rs, Register rt, int saPlusOne) argument
719 Lb(Register rt, Register rs, uint16_t imm16) argument
723 Lh(Register rt, Register rs, uint16_t imm16) argument
727 Lw(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label) argument
734 Lw(Register rt, Register rs, uint16_t imm16) argument
738 Lwl(Register rt, Register rs, uint16_t imm16) argument
743 Lwr(Register rt, Register rs, uint16_t imm16) argument
748 Lbu(Register rt, Register rs, uint16_t imm16) argument
752 Lhu(Register rt, Register rs, uint16_t imm16) argument
762 Lui(Register rt, uint16_t imm16) argument
766 Aui(Register rt, Register rs, uint16_t imm16) argument
771 AddUpper(Register rt, Register rs, uint16_t imm16, Register tmp) argument
801 Sb(Register rt, Register rs, uint16_t imm16) argument
805 Sh(Register rt, Register rs, uint16_t imm16) argument
809 Sw(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label) argument
816 Sw(Register rt, Register rs, uint16_t imm16) argument
820 Swl(Register rt, Register rs, uint16_t imm16) argument
825 Swr(Register rt, Register rs, uint16_t imm16) argument
830 LlR2(Register rt, Register base, int16_t imm16) argument
835 ScR2(Register rt, Register base, int16_t imm16) argument
840 LlR6(Register rt, Register base, int16_t imm9) argument
846 ScR6(Register rt, Register base, int16_t imm9) argument
852 Slt(Register rd, Register rs, Register rt) argument
856 Sltu(Register rd, Register rs, Register rt) argument
860 Slti(Register rt, Register rs, uint16_t imm16) argument
864 Sltiu(Register rt, Register rs, uint16_t imm16) argument
876 Beq(Register rs, Register rt, uint16_t imm16) argument
880 Bne(Register rs, Register rt, uint16_t imm16) argument
884 Beqz(Register rt, uint16_t imm16) argument
888 Bnez(Register rt, uint16_t imm16) argument
892 Bltz(Register rt, uint16_t imm16) argument
896 Bgez(Register rt, uint16_t imm16) argument
900 Blez(Register rt, uint16_t imm16) argument
904 Bgtz(Register rt, uint16_t imm16) argument
1004 Jic(Register rt, uint16_t imm16) argument
1009 Jialc(Register rt, uint16_t imm16) argument
1014 Bltc(Register rs, Register rt, uint16_t imm16) argument
1022 Bltzc(Register rt, uint16_t imm16) argument
1028 Bgtzc(Register rt, uint16_t imm16) argument
1034 Bgec(Register rs, Register rt, uint16_t imm16) argument
1042 Bgezc(Register rt, uint16_t imm16) argument
1048 Blezc(Register rt, uint16_t imm16) argument
1054 Bltuc(Register rs, Register rt, uint16_t imm16) argument
1062 Bgeuc(Register rs, Register rt, uint16_t imm16) argument
1070 Beqc(Register rs, Register rt, uint16_t imm16) argument
1078 Bnec(Register rs, Register rt, uint16_t imm16) argument
1108 EmitBcondR2(BranchCondition cond, Register rs, Register rt, uint16_t imm16) argument
1162 EmitBcondR6(BranchCondition cond, Register rs, Register rt, uint32_t imm16_21) argument
1586 MovzS(FRegister fd, FRegister fs, Register rt) argument
1592 MovzD(FRegister fd, FRegister fs, Register rt) argument
1598 MovnS(FRegister fd, FRegister fs, Register rt) argument
1604 MovnD(FRegister fd, FRegister fs, Register rt) argument
1727 Mfc1(Register rt, FRegister fs) argument
1734 Mtc1(Register rt, FRegister fs) argument
1747 Mfhc1(Register rt, FRegister fs) argument
1754 Mthc1(Register rt, FRegister fs) argument
1759 MoveFromFpuHigh(Register rt, FRegister fs) argument
1768 MoveToFpuHigh(Register rt, FRegister fs) argument
1839 PopAndReturn(Register rd, Register rt) argument
2858 Addiu32(Register rt, Register rs, int32_t value, Register temp) argument
4290 Beq(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4294 Bne(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4298 Beqz(Register rt, MipsLabel* label, bool is_bare) argument
4302 Bnez(Register rt, MipsLabel* label, bool is_bare) argument
4306 Bltz(Register rt, MipsLabel* label, bool is_bare) argument
4310 Bgez(Register rt, MipsLabel* label, bool is_bare) argument
4314 Blez(Register rt, MipsLabel* label, bool is_bare) argument
4318 Bgtz(Register rt, MipsLabel* label, bool is_bare) argument
4350 GenerateSltForCondBranch(bool unsigned_slt, Register rs, Register rt) argument
4370 Blt(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4380 Bge(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4392 Bltu(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4402 Bgeu(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4440 Beqc(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4444 Bnec(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4448 Beqzc(Register rt, MipsLabel* label, bool is_bare) argument
4452 Bnezc(Register rt, MipsLabel* label, bool is_bare) argument
4456 Bltzc(Register rt, MipsLabel* label, bool is_bare) argument
4460 Bgezc(Register rt, MipsLabel* label, bool is_bare) argument
4464 Blezc(Register rt, MipsLabel* label, bool is_bare) argument
4468 Bgtzc(Register rt, MipsLabel* label, bool is_bare) argument
4472 Bltc(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4476 Bgec(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4480 Bltuc(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
4484 Bgeuc(Register rs, Register rt, MipsLabel* label, bool is_bare) argument
[all...] |
| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.h | 446 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
447 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
448 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
449 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
450 void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
451 void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
453 void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
454 void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
455 void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
456 void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
[all...] |
| H A D | assembler_mips64.cc | 99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, argument
102 CHECK_NE(rt, kNoGpuRegister);
106 static_cast<uint32_t>(rt) << kRtShift |
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, argument
128 CHECK_NE(rt, kNoGpuRegister);
132 static_cast<uint32_t>(rt) << kRtShift |
139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { argument
141 CHECK_NE(rt, kNoGpuRegister);
144 static_cast<uint32_t>(rt) << kRtShift |
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { argument
307 Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
311 Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
315 Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
319 Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
323 Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
327 MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
331 MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
335 DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
339 ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
343 DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
347 ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
351 Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
355 Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
359 Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
363 Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
367 Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
371 Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
375 And(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
379 Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
383 Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
387 Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
391 Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
395 Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
399 Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
403 Bitswap(GpuRegister rd, GpuRegister rt) argument
407 Dbitswap(GpuRegister rd, GpuRegister rt) argument
411 Seb(GpuRegister rd, GpuRegister rt) argument
415 Seh(GpuRegister rd, GpuRegister rt) argument
419 Dsbh(GpuRegister rd, GpuRegister rt) argument
423 Dshd(GpuRegister rd, GpuRegister rt) argument
427 Dext(GpuRegister rt, GpuRegister rs, int pos, int size) argument
433 Ins(GpuRegister rd, GpuRegister rt, int pos, int size) argument
440 Dinsm(GpuRegister rt, GpuRegister rs, int pos, int size) argument
447 Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) argument
454 Dins(GpuRegister rt, GpuRegister rs, int pos, int size) argument
461 DblIns(GpuRegister rt, GpuRegister rs, int pos, int size) argument
471 Lsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) argument
477 Dlsa(GpuRegister rd, GpuRegister rs, GpuRegister rt, int saPlusOne) argument
483 Wsbh(GpuRegister rd, GpuRegister rt) argument
487 Sc(GpuRegister rt, GpuRegister base, int16_t imm9) argument
492 Scd(GpuRegister rt, GpuRegister base, int16_t imm9) argument
497 Ll(GpuRegister rt, GpuRegister base, int16_t imm9) argument
502 Lld(GpuRegister rt, GpuRegister base, int16_t imm9) argument
507 Sll(GpuRegister rd, GpuRegister rt, int shamt) argument
511 Srl(GpuRegister rd, GpuRegister rt, int shamt) argument
515 Rotr(GpuRegister rd, GpuRegister rt, int shamt) argument
519 Sra(GpuRegister rd, GpuRegister rt, int shamt) argument
523 Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
527 Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
531 Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
535 Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
539 Dsll(GpuRegister rd, GpuRegister rt, int shamt) argument
543 Dsrl(GpuRegister rd, GpuRegister rt, int shamt) argument
547 Drotr(GpuRegister rd, GpuRegister rt, int shamt) argument
551 Dsra(GpuRegister rd, GpuRegister rt, int shamt) argument
555 Dsll32(GpuRegister rd, GpuRegister rt, int shamt) argument
559 Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) argument
563 Drotr32(GpuRegister rd, GpuRegister rt, int shamt) argument
567 Dsra32(GpuRegister rd, GpuRegister rt, int shamt) argument
571 Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
575 Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
579 Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
583 Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) argument
587 Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
591 Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
595 Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
599 Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
603 Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
607 Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
611 Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
630 Lui(GpuRegister rt, uint16_t imm16) argument
634 Aui(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
638 Daui(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
656 Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
660 Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
664 Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
668 Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
672 Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
676 Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
680 Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
684 Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) argument
688 Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
692 Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) argument
741 Jic(GpuRegister rt, uint16_t imm16) argument
745 Jialc(GpuRegister rt, uint16_t imm16) argument
749 Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
756 Bltzc(GpuRegister rt, uint16_t imm16) argument
761 Bgtzc(GpuRegister rt, uint16_t imm16) argument
766 Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
773 Bgezc(GpuRegister rt, uint16_t imm16) argument
778 Blezc(GpuRegister rt, uint16_t imm16) argument
783 Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
790 Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
797 Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
804 Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
829 Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
833 Bne(GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
837 Beqz(GpuRegister rt, uint16_t imm16) argument
841 Bnez(GpuRegister rt, uint16_t imm16) argument
845 Bltz(GpuRegister rt, uint16_t imm16) argument
849 Bgez(GpuRegister rt, uint16_t imm16) argument
853 Blez(GpuRegister rt, uint16_t imm16) argument
857 Bgtz(GpuRegister rt, uint16_t imm16) argument
861 EmitBcondR6(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint32_t imm16_21) argument
928 EmitBcondR2(BranchCondition cond, GpuRegister rs, GpuRegister rt, uint16_t imm16) argument
1265 Mfc1(GpuRegister rt, FpuRegister fs) argument
1269 Mfhc1(GpuRegister rt, FpuRegister fs) argument
1273 Mtc1(GpuRegister rt, FpuRegister fs) argument
1277 Mthc1(GpuRegister rt, FpuRegister fs) argument
1281 Dmfc1(GpuRegister rt, FpuRegister fs) argument
1285 Dmtc1(GpuRegister rt, FpuRegister fs) argument
2305 Addiu32(GpuRegister rt, GpuRegister rs, int32_t value) argument
2320 Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) argument
3260 Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
3264 Bltzc(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3268 Bgtzc(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3272 Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
3276 Bgezc(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3280 Blezc(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3284 Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
3288 Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
3292 Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
3296 Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
3316 Bltz(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3321 Bgtz(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3326 Bgez(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3331 Blez(GpuRegister rt, Mips64Label* label, bool is_bare) argument
3336 Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
3341 Bne(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) argument
[all...] |
| H A D | assembler_mips64_test.cc | 2591 void Dinsu(mips64::GpuRegister rt, mips64::GpuRegister rs, int pos, int size) { argument
2598 regs_[rt] = (regs_[rt] & dsk_mask) | ((regs_[rs] & src_mask) << pos);
2600 void Dsll(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { argument
2601 regs_[rd] = regs_[rt] << (shamt & 0x1f);
2603 void Dsll32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { argument
2604 regs_[rd] = regs_[rt] << (32 + (shamt & 0x1f));
2606 void Dsrl(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { argument
2607 regs_[rd] = regs_[rt] >> (shamt & 0x1f);
2609 void Dsrl32(mips64::GpuRegister rd, mips64::GpuRegister rt, in argument
[all...] |
| /art/runtime/interpreter/mterp/mips/ |
| H A D | header.S | 160 #define SEB(rd, rt) \
161 seb rd, rt
162 #define SEH(rd, rt) \
163 seh rd, rt
167 #define SEB(rd, rt) \
168 sll rd, rt, 24; \
170 #define SEH(rd, rt) \
171 sll rd, rt, 16; \
188 #define JR(rt) \
189 jic rt,
[all...] |
| /art/disassembler/ |
| H A D | disassembler_mips.cc | 522 uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type. local
564 args << "cc" << (rt >> 2);
655 case 'T': args << RegName(rt); break;
656 case 't': args << 'f' << rt; break; local
661 case 'n': args << 'w' << rt; break; local
819 if (((op == 0x36 || op == 0x3E) && rs == 0 && rt != 0) && // ji[al]c
822 ((last_instr_ >> 21) & 0x1F) == rt) {
|
| /art/runtime/interpreter/mterp/out/ |
| H A D | mterp_mips.S | 167 #define SEB(rd, rt) \
168 seb rd, rt
169 #define SEH(rd, rt) \
170 seh rd, rt
174 #define SEB(rd, rt) \
175 sll rd, rt, 24; \
177 #define SEH(rd, rt) \
178 sll rd, rt, 16; \
195 #define JR(rt) \
196 jic rt,
[all...] |
| /art/compiler/optimizing/ |
| H A D | loop_optimization.cc | 927 HInstruction* rt = Insert( local
932 HSelect(rt, vtc, graph_->GetConstant(induc_type, 0), kNoDexPc));
|
| H A D | code_generator_arm_vixl.cc | 134 static inline bool CanEmitNarrowLdr(vixl32::Register rt, vixl32::Register rn, uint32_t offset) { argument
135 return rt.IsLow() && rn.IsLow() && offset < 32u;
|