Searched refs:s0 (Results 1 - 25 of 43) sorted by relevance

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/art/test/StaticsFromCode/
H A DStaticsFromCode.java18 static final Object s0 = "android"; field in class:StaticsFromCode
21 return s0;
/art/runtime/arch/
H A Dmemcmp16.cc22 int32_t memcmp16_generic_static(const uint16_t* s0, const uint16_t* s1, size_t count);
23 int32_t memcmp16_generic_static(const uint16_t* s0, const uint16_t* s1, size_t count) { argument
25 if (s0[i] != s1[i]) {
26 return static_cast<int32_t>(s0[i]) - static_cast<int32_t>(s1[i]);
36 int32_t MemCmp16Testing(const uint16_t* s0, const uint16_t* s1, size_t count) { argument
37 return MemCmp16(s0, s1, count);
H A Dmemcmp16.h35 extern "C" uint32_t __memcmp16(const uint16_t* s0, const uint16_t* s1, size_t count);
41 static inline int32_t MemCmp16(const uint16_t* s0, const uint16_t* s1, size_t count) { argument
43 if (s0[i] != s1[i]) {
44 return static_cast<int32_t>(s0[i]) - static_cast<int32_t>(s1[i]);
50 extern "C" int32_t memcmp16_generic_static(const uint16_t* s0, const uint16_t* s1, size_t count);
60 int32_t MemCmp16Testing(const uint16_t* s0, const uint16_t* s1, size_t count);
H A Dmemcmp16_test.cc38 int32_t memcmp16_compare(const uint16_t* s0, const uint16_t* s1, size_t count) { argument
40 if (s0[i] != s1[i]) {
41 return static_cast<int32_t>(s0[i]) - static_cast<int32_t>(s1[i]);
/art/runtime/interpreter/mterp/arm64/
H A Dfbinop.S6 * form: <op> s0, s0, s1
13 GET_VREG s0, w0
14 $instr // s0<- op
18 SET_VREG s0, w1
H A Dop_rem_float_2addr.S5 GET_VREG s0, w9
10 SET_VREG s0, w9
H A Dfbinop2addr.S4 * "s2 = s0 op s1".
12 GET_VREG s0, w9
/art/test/Statics/
H A DStatics.java18 static final boolean s0 = true; field in class:Statics
29 return s0;
/art/runtime/arch/arm/
H A Dinstruction_set_features_assembly_tests.S54 vmov r1, s0
56 // The T32 encoding for vrinta.f32.f32 s0,s0 is two 16bit words: 0xfeb8,0x0a40, with little
62 vmov s0, r1
/art/runtime/interpreter/mterp/arm/
H A DfunopNarrower.S3 * "instr" line that specifies an instruction that performs "s0 = op d0".
13 $instr @ s0<- op
16 fsts s0, [r9] @ vA<- s0
H A Dfbinop2addr.S4 * "s2 = s0 op s1".
15 flds s0, [r9] @ s0<- vA
H A Dfunop.S3 * line that specifies an instruction that performs "s1 = op s0".
10 flds s0, [r3] @ s0<- vB
H A DfunopWider.S3 * "instr" line that specifies an instruction that performs "d0 = op s0".
10 flds s0, [r3] @ s0<- vB
H A Dop_cmpg_float.S24 flds s0, [r2] @ s0<- vBB
26 vcmpe.f32 s0, s1 @ compare (vBB, vCC)
H A Dop_cmpl_float.S24 flds s0, [r2] @ s0<- vBB
26 vcmpe.f32 s0, s1 @ compare (vBB, vCC)
H A Dfbinop.S3 * specifies an instruction that performs "s2 = s0 op s1". Because we
16 flds s0, [r2] @ s0<- vBB
H A Dop_long_to_double.S17 vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl)
/art/test/004-StackWalk/src/
H A DMain.java26 String s0 = new String("0");
48 s += s0;
/art/runtime/arch/mips64/
H A Dasm_support_mips64.S25 #define rSUSPEND $s0
/art/runtime/interpreter/mterp/mips64/
H A Dentry.S48 sd s0, STACK_OFFSET_S0(sp)
H A Dheader.S38 #define s0 $$16 /* saved across subroutine calls (callee saved) */ define
81 s0 rPC interpreted program counter, used for fetching instructions
92 #define rPC s0
93 #define CFI_DEX 16 // DWARF register number of the register holding dex-pc (s0).
H A Dfooter.S259 ld s0, STACK_OFFSET_S0(sp)
/art/runtime/arch/mips/
H A Dasm_support_mips.S25 #define rSUSPEND $s0
/art/runtime/interpreter/mterp/out/
H A Dmterp_arm64.S60 v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit).
3426 * "instr" line that specifies an instruction that performs "s0 = op w0".
3436 scvtf s0, w0 // d0<- op
3438 SET_VREG s0, w4 // vA<- d0
3492 * "instr" line that specifies an instruction that performs "s0 = op x0".
3501 scvtf s0, x0 // d0<- op
3503 SET_VREG s0, w4 // vA<- d0
3536 * "instr" line that specifies an instruction that performs "w0 = op s0".
3544 GET_VREG s0, w3
3546 fcvtzs w0, s0 // d
[all...]
H A Dmterp_arm.S59 s0-s15 (d0-d7, q0-a3) do not need to be.
65 VFP: single-precision results in s0, double-precision results in d0.
1269 flds s0, [r2] @ s0<- vBB
1271 vcmpe.f32 s0, s1 @ compare (vBB, vCC)
1308 flds s0, [r2] @ s0<- vBB
1310 vcmpe.f32 s0, s1 @ compare (vBB, vCC)
3558 * line that specifies an instruction that performs "s1 = op s0".
3565 flds s0, [r
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