Searched refs:IsSP (Results 1 - 12 of 12) sorted by relevance

/external/vixl/src/aarch64/
H A Doperands-aarch64.cc308 VIXL_ASSERT(!reg.IsSP());
319 VIXL_ASSERT(!reg.IsSP());
406 VIXL_ASSERT(!regoffset.IsSP());
426 VIXL_ASSERT(regoffset.Is64Bits() && !regoffset.IsSP());
453 VIXL_ASSERT(regoffset_.Is64Bits() && !regoffset_.IsSP());
467 VIXL_ASSERT(!regoffset_.IsSP());
H A Dmacro-assembler-aarch64.cc467 temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd;
498 if (rd.IsSP()) {
514 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) {
521 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) {
880 PreShiftImmMode mode = rn.IsSP() ? kNoShift : kAnyShift;
1220 VIXL_ASSERT(!rd.IsZero() && !rd.IsSP());
1221 VIXL_ASSERT(left.IsImmediate() || !left.GetRegister().IsSP());
1222 VIXL_ASSERT(right.IsImmediate() || !right.GetRegister().IsSP());
1705 if (rd.IsSP()) {
1709 } else if (rn.IsSP()) {
[all...]
H A Doperands-aarch64.h183 bool IsSP() const {
H A Dassembler-aarch64.cc2036 if (rd.IsSP() || rm.IsSP()) {
3962 if (rn.IsSP() || rd.IsSP()) {
3963 VIXL_ASSERT(!(rd.IsSP() && (S == SetFlags)));
/external/v8/src/arm64/
H A Dassembler-arm64-inl.h145 inline bool CPURegister::IsSP() const { function in class:v8::internal::CPURegister
337 DCHECK(!reg.IsSP());
349 DCHECK(!reg.IsSP());
465 DCHECK(!regoffset.IsSP());
480 DCHECK(regoffset.Is64Bits() && !regoffset.IsSP());
504 DCHECK(regoffset_.Is64Bits() && !regoffset_.IsSP());
518 DCHECK(!regoffset_.IsSP());
H A Dassembler-arm64.cc1779 if (rd.IsSP() || rm.IsSP()) {
2272 if (rn.IsSP() || rd.IsSP()) {
2273 DCHECK(!(rd.IsSP() && (S == SetFlags)));
H A Dmacro-assembler-arm64.cc206 Register temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd;
232 if (rd.IsSP()) {
249 Register dst = (rd.IsSP()) ? temps.AcquireSameSizeAs(rd) : rd;
290 DCHECK(rd.IsSP());
419 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) {
424 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) {
H A Dmacro-assembler-arm64-inl.h460 DCHECK(!rd.IsSP() && rd.Is64Bits());
472 DCHECK(!rd.IsSP());
H A Dassembler-arm64.h114 bool IsSP() const;
/external/vixl/src/aarch32/
H A Dassembler-aarch32.cc18219 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18250 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18264 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&
18280 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18310 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18323 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() &&
18599 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18624 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18640 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) {
18657 !rm.IsPC() && !rm.IsSP()
[all...]
H A Dinstructions-aarch32.h146 bool IsSP() const { return GetCode() == kSpCode; }
H A Dmacro-assembler-aarch32.h1073 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) ||
1079 !operand.GetBaseRegister().IsSP() &&
1082 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() &&
2083 operand.GetBaseRegister().IsSP() &&
4415 operand.GetBaseRegister().IsSP() &&

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