Searched refs:MCInst_getOperand (Results 1 - 23 of 23) sorted by relevance

/external/capstone/arch/Sparc/
H A DSparcGenAsmWriter.inc1219 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1228 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1229 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1235 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1236 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1242 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1243 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1249 MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1250 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1256 MCOperand_isImm(MCInst_getOperand(M
[all...]
H A DSparcInstPrinter.c113 if (!MCOperand_isReg(MCInst_getOperand(MI, 0)))
116 switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) {
119 if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
120 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
121 switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) {
145 (!MCOperand_isReg(MCInst_getOperand(MI, 0))) ||
146 (MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0))
169 MCOperand *MO = MCInst_getOperand(MI, opNum);
306 MO = MCInst_getOperand(MI, opNum + 1);
326 int CC = (int)MCOperand_getImm(MCInst_getOperand(M
[all...]
/external/capstone/arch/PowerPC/
H A DPPCGenAsmWriter.inc4288 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
4297 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
4298 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
4299 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4306 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
4307 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
4308 MCOperand_getReg(MCInst_getOperand(MI, 1)) == PPC_CR0) {
4314 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
4315 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14 &&
4316 MCOperand_isReg(MCInst_getOperand(M
[all...]
H A DPPCInstPrinter.c88 unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
89 unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
90 unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
128 MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) {
138 unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
139 unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
158 int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2));
160 MCOperand_setImm(MCInst_getOperand(MI, 2),bd);
164 if (MCOperand_isImm(MCInst_getOperand(M
[all...]
/external/capstone/arch/AArch64/
H A DAArch64GenAsmWriter.inc7078 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
7087 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7088 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7097 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7098 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
7100 MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
7102 MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
7103 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
7109 MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR &&
7110 MCOperand_isReg(MCInst_getOperand(M
[all...]
H A DAArch64InstPrinter.c80 MCOperand *Op0 = MCInst_getOperand(MI, 0);
81 MCOperand *Op1 = MCInst_getOperand(MI, 1);
82 MCOperand *Op2 = MCInst_getOperand(MI, 2);
83 MCOperand *Op3 = MCInst_getOperand(MI, 3);
246 MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0
247 MCOperand *Op2 = MCInst_getOperand(MI, 2);
248 int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3));
249 int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4));
327 MCOperand *Op1 = MCInst_getOperand(MI, 0);
328 MCOperand *Cn = MCInst_getOperand(M
[all...]
H A DAArch64Disassembler.c932 MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0));
/external/capstone/arch/ARM/
H A DARMGenAsmWriter.inc8694 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
8703 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8705 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8712 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8714 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8715 MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 0))) {
8723 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
8725 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
8732 MCOperand_isReg(MCInst_getOperand(M
[all...]
H A DARMInstPrinter.c415 switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) {
444 MCOperand *Dst = MCInst_getOperand(MI, 0);
445 MCOperand *MO1 = MCInst_getOperand(MI, 1);
446 MCOperand *MO2 = MCInst_getOperand(MI, 2);
447 MCOperand *MO3 = MCInst_getOperand(MI, 3);
483 MCOperand *Dst = MCInst_getOperand(MI, 0);
484 MCOperand *MO1 = MCInst_getOperand(MI, 1);
485 MCOperand *MO2 = MCInst_getOperand(MI, 2);
529 if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
544 if (MCOperand_getReg(MCInst_getOperand(M
[all...]
H A DARMDisassembler.c673 MCOperand_setImm(MCInst_getOperand(MI, i), CC);
675 MCOperand_setReg(MCInst_getOperand(MI, i+1), 0);
677 MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR);
745 Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
746 Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
1258 WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0));
/external/capstone/arch/SystemZ/
H A DSystemZInstPrinter.c117 int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
140 uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
157 int8_t Value = (int8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
181 uint8_t Value = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
198 int16_t Value = (int16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
222 uint16_t Value = (uint16_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
239 int32_t Value = (int32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
263 uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
280 int64_t Value = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
293 MCOperand *MO = MCInst_getOperand(M
[all...]
/external/capstone/arch/Mips/
H A DMipsGenAsmWriter.inc5061 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
5070 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5072 MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5074 MCOperand_getReg(MCInst_getOperand(MI, 2)) == Mips_ZERO) {
5082 MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
5090 MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
5098 MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
5106 MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_CC0) {
5114 MCOperand_getReg(MCInst_getOperand(MI, 0)) == Mips_FCC0) {
5122 MCOperand_getReg(MCInst_getOperand(M
[all...]
H A DMipsInstPrinter.c107 return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
108 MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
191 Op = MCInst_getOperand(MI, OpNo);
247 MCOperand *MO = MCInst_getOperand(MI, opNum);
272 MCOperand *MO = MCInst_getOperand(MI, opNum);
314 MCOperand *MO = MCInst_getOperand(MI, opNum);
H A DMipsDisassembler.c1305 int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
/external/capstone/
H A DMCInst.h126 MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
H A DMCInst.c64 MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) function
/external/capstone/arch/X86/
H A DX86ATTInstPrinter.c166 int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7;
190 int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
230 int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
247 MCOperand *Op = MCInst_getOperand(MI, OpNo);
282 SegReg = MCInst_getOperand(MI, Op+1);
383 MCOperand *DispSpec = MCInst_getOperand(MI, Op);
384 MCOperand *SegReg = MCInst_getOperand(MI, Op+1);
455 MCOperand *Op = MCInst_getOperand(MI, OpNo);
497 MCOperand *Op = MCInst_getOperand(MI, OpNo);
674 MCOperand *BaseReg = MCInst_getOperand(M
[all...]
H A DX86IntelInstPrinter.c188 int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 7;
212 int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
252 int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
273 MCOperand *Op = MCInst_getOperand(MI, OpNo);
308 SegReg = MCInst_getOperand(MI, Op+1);
412 MCOperand *DispSpec = MCInst_getOperand(MI, Op);
413 MCOperand *SegReg = MCInst_getOperand(MI, Op + 1);
542 MCOperand *Op = MCInst_getOperand(MI, OpNo);
591 MCOperand *Op = MCInst_getOperand(MI, OpNo);
769 MCOperand *BaseReg = MCInst_getOperand(M
[all...]
H A DX86GenAsmWriter1_reduce.inc2773 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
2781 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
2782 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
2790 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
2791 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
H A DX86GenAsmWriter_reduce.inc3087 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
3095 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3096 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
3104 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3105 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
H A DX86GenAsmWriter.inc15653 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
15662 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
15663 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
15671 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
15672 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
15680 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
H A DX86GenAsmWriter1.inc15050 #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
15059 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
15060 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
15068 MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
15069 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 10) {
15077 MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
/external/capstone/arch/XCore/
H A DXCoreInstPrinter.c240 _printOperand(MI, MCInst_getOperand(MI, OpNum), O);

Completed in 328 milliseconds