1//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the subtarget options of a Target machine. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15#define LLVM_TARGET_TARGETSUBTARGETINFO_H 16 17#include "llvm/MC/MCSubtargetInfo.h" 18#include "llvm/Target/TargetMachine.h" 19 20namespace llvm { 21 22class SDep; 23class SUnit; 24class TargetRegisterClass; 25template <typename T> class SmallVectorImpl; 26 27//===----------------------------------------------------------------------===// 28/// 29/// TargetSubtargetInfo - Generic base class for all target subtargets. All 30/// Target-specific options that control code generation and printing should 31/// be exposed through a TargetSubtargetInfo-derived class. 32/// 33class TargetSubtargetInfo : public MCSubtargetInfo { 34 TargetSubtargetInfo(const TargetSubtargetInfo&); // DO NOT IMPLEMENT 35 void operator=(const TargetSubtargetInfo&); // DO NOT IMPLEMENT 36protected: // Can only create subclasses... 37 TargetSubtargetInfo(); 38public: 39 // AntiDepBreakMode - Type of anti-dependence breaking that should 40 // be performed before post-RA scheduling. 41 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 42 typedef SmallVectorImpl<TargetRegisterClass*> RegClassVector; 43 44 virtual ~TargetSubtargetInfo(); 45 46 /// getSpecialAddressLatency - For targets where it is beneficial to 47 /// backschedule instructions that compute addresses, return a value 48 /// indicating the number of scheduling cycles of backscheduling that 49 /// should be attempted. 50 virtual unsigned getSpecialAddressLatency() const { return 0; } 51 52 // enablePostRAScheduler - If the target can benefit from post-regalloc 53 // scheduling and the specified optimization level meets the requirement 54 // return true to enable post-register-allocation scheduling. In 55 // CriticalPathRCs return any register classes that should only be broken 56 // if on the critical path. 57 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 58 AntiDepBreakMode& Mode, 59 RegClassVector& CriticalPathRCs) const; 60 // adjustSchedDependency - Perform target specific adjustments to 61 // the latency of a schedule dependency. 62 virtual void adjustSchedDependency(SUnit *def, SUnit *use, 63 SDep& dep) const { } 64}; 65 66} // End llvm namespace 67 68#endif 69