1//=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the ARM implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMFrameLowering.h" 15#include "ARMBaseInstrInfo.h" 16#include "ARMBaseRegisterInfo.h" 17#include "ARMMachineFunctionInfo.h" 18#include "llvm/CallingConv.h" 19#include "llvm/Function.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/RegisterScavenging.h" 26#include "llvm/Target/TargetOptions.h" 27 28using namespace llvm; 29 30/// hasFP - Return true if the specified function should have a dedicated frame 31/// pointer register. This is true if the function has variable sized allocas 32/// or if frame pointer elimination is disabled. 33bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 34 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 35 36 // Mac OS X requires FP not to be clobbered for backtracing purpose. 37 if (STI.isTargetDarwin()) 38 return true; 39 40 const MachineFrameInfo *MFI = MF.getFrameInfo(); 41 // Always eliminate non-leaf frame pointers. 42 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) || 43 RegInfo->needsStackRealignment(MF) || 44 MFI->hasVarSizedObjects() || 45 MFI->isFrameAddressTaken()); 46} 47 48/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 49/// not required, we reserve argument space for call sites in the function 50/// immediately on entry to the current function. This eliminates the need for 51/// add/sub sp brackets around call sites. Returns true if the call frame is 52/// included as part of the stack frame. 53bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 54 const MachineFrameInfo *FFI = MF.getFrameInfo(); 55 unsigned CFSize = FFI->getMaxCallFrameSize(); 56 // It's not always a good idea to include the call frame as part of the 57 // stack frame. ARM (especially Thumb) has small immediate offset to 58 // address the stack frame. So a large call frame can cause poor codegen 59 // and may even makes it impossible to scavenge a register. 60 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 61 return false; 62 63 return !MF.getFrameInfo()->hasVarSizedObjects(); 64} 65 66/// canSimplifyCallFramePseudos - If there is a reserved call frame, the 67/// call frame pseudos can be simplified. Unlike most targets, having a FP 68/// is not sufficient here since we still may reference some objects via SP 69/// even when FP is available in Thumb2 mode. 70bool 71ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { 72 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 73} 74 75static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 76 for (unsigned i = 0; CSRegs[i]; ++i) 77 if (Reg == CSRegs[i]) 78 return true; 79 return false; 80} 81 82static bool isCSRestore(MachineInstr *MI, 83 const ARMBaseInstrInfo &TII, 84 const unsigned *CSRegs) { 85 // Integer spill area is handled with "pop". 86 if (MI->getOpcode() == ARM::LDMIA_RET || 87 MI->getOpcode() == ARM::t2LDMIA_RET || 88 MI->getOpcode() == ARM::LDMIA_UPD || 89 MI->getOpcode() == ARM::t2LDMIA_UPD || 90 MI->getOpcode() == ARM::VLDMDIA_UPD) { 91 // The first two operands are predicates. The last two are 92 // imp-def and imp-use of SP. Check everything in between. 93 for (int i = 5, e = MI->getNumOperands(); i != e; ++i) 94 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 95 return false; 96 return true; 97 } 98 if ((MI->getOpcode() == ARM::LDR_POST_IMM || 99 MI->getOpcode() == ARM::LDR_POST_REG || 100 MI->getOpcode() == ARM::t2LDR_POST) && 101 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && 102 MI->getOperand(1).getReg() == ARM::SP) 103 return true; 104 105 return false; 106} 107 108static void 109emitSPUpdate(bool isARM, 110 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 111 DebugLoc dl, const ARMBaseInstrInfo &TII, 112 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 113 if (isARM) 114 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 115 ARMCC::AL, 0, TII, MIFlags); 116 else 117 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 118 ARMCC::AL, 0, TII, MIFlags); 119} 120 121void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { 122 MachineBasicBlock &MBB = MF.front(); 123 MachineBasicBlock::iterator MBBI = MBB.begin(); 124 MachineFrameInfo *MFI = MF.getFrameInfo(); 125 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 126 const ARMBaseRegisterInfo *RegInfo = 127 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 128 const ARMBaseInstrInfo &TII = 129 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 130 assert(!AFI->isThumb1OnlyFunction() && 131 "This emitPrologue does not support Thumb1!"); 132 bool isARM = !AFI->isThumbFunction(); 133 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 134 unsigned NumBytes = MFI->getStackSize(); 135 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 136 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 137 unsigned FramePtr = RegInfo->getFrameRegister(MF); 138 139 // Determine the sizes of each callee-save spill areas and record which frame 140 // belongs to which callee-save spill areas. 141 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 142 int FramePtrSpillFI = 0; 143 144 // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue. 145 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 146 return; 147 148 // Allocate the vararg register save area. This is not counted in NumBytes. 149 if (VARegSaveSize) 150 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize, 151 MachineInstr::FrameSetup); 152 153 if (!AFI->hasStackFrame()) { 154 if (NumBytes != 0) 155 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 156 MachineInstr::FrameSetup); 157 return; 158 } 159 160 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 161 unsigned Reg = CSI[i].getReg(); 162 int FI = CSI[i].getFrameIdx(); 163 switch (Reg) { 164 case ARM::R4: 165 case ARM::R5: 166 case ARM::R6: 167 case ARM::R7: 168 case ARM::LR: 169 if (Reg == FramePtr) 170 FramePtrSpillFI = FI; 171 AFI->addGPRCalleeSavedArea1Frame(FI); 172 GPRCS1Size += 4; 173 break; 174 case ARM::R8: 175 case ARM::R9: 176 case ARM::R10: 177 case ARM::R11: 178 if (Reg == FramePtr) 179 FramePtrSpillFI = FI; 180 if (STI.isTargetDarwin()) { 181 AFI->addGPRCalleeSavedArea2Frame(FI); 182 GPRCS2Size += 4; 183 } else { 184 AFI->addGPRCalleeSavedArea1Frame(FI); 185 GPRCS1Size += 4; 186 } 187 break; 188 default: 189 AFI->addDPRCalleeSavedAreaFrame(FI); 190 DPRCSSize += 8; 191 } 192 } 193 194 // Move past area 1. 195 if (GPRCS1Size > 0) MBBI++; 196 197 // Set FP to point to the stack slot that contains the previous FP. 198 // For Darwin, FP is R7, which has now been stored in spill area 1. 199 // Otherwise, if this is not Darwin, all the callee-saved registers go 200 // into spill area 1, including the FP in R11. In either case, it is 201 // now safe to emit this assignment. 202 bool HasFP = hasFP(MF); 203 if (HasFP) { 204 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 205 MachineInstrBuilder MIB = 206 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 207 .addFrameIndex(FramePtrSpillFI).addImm(0) 208 .setMIFlag(MachineInstr::FrameSetup); 209 AddDefaultCC(AddDefaultPred(MIB)); 210 } 211 212 // Move past area 2. 213 if (GPRCS2Size > 0) MBBI++; 214 215 // Determine starting offsets of spill areas. 216 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 217 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 218 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 219 if (HasFP) 220 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 221 NumBytes); 222 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 223 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 224 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 225 226 // Move past area 3. 227 if (DPRCSSize > 0) { 228 MBBI++; 229 // Since vpush register list cannot have gaps, there may be multiple vpush 230 // instructions in the prologue. 231 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) 232 MBBI++; 233 } 234 235 NumBytes = DPRCSOffset; 236 if (NumBytes) { 237 // Adjust SP after all the callee-save spills. 238 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 239 MachineInstr::FrameSetup); 240 if (HasFP && isARM) 241 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 242 // Note it's not safe to do this in Thumb2 mode because it would have 243 // taken two instructions: 244 // mov sp, r7 245 // sub sp, #24 246 // If an interrupt is taken between the two instructions, then sp is in 247 // an inconsistent state (pointing to the middle of callee-saved area). 248 // The interrupt handler can end up clobbering the registers. 249 AFI->setShouldRestoreSPFromFP(true); 250 } 251 252 if (STI.isTargetELF() && hasFP(MF)) 253 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 254 AFI->getFramePtrSpillOffset()); 255 256 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 257 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 258 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 259 260 // If we need dynamic stack realignment, do it here. Be paranoid and make 261 // sure if we also have VLAs, we have a base pointer for frame access. 262 if (RegInfo->needsStackRealignment(MF)) { 263 unsigned MaxAlign = MFI->getMaxAlignment(); 264 assert (!AFI->isThumb1OnlyFunction()); 265 if (!AFI->isThumbFunction()) { 266 // Emit bic sp, sp, MaxAlign 267 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 268 TII.get(ARM::BICri), ARM::SP) 269 .addReg(ARM::SP, RegState::Kill) 270 .addImm(MaxAlign-1))); 271 } else { 272 // We cannot use sp as source/dest register here, thus we're emitting the 273 // following sequence: 274 // mov r4, sp 275 // bic r4, r4, MaxAlign 276 // mov sp, r4 277 // FIXME: It will be better just to find spare register here. 278 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 279 .addReg(ARM::SP, RegState::Kill)); 280 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 281 TII.get(ARM::t2BICri), ARM::R4) 282 .addReg(ARM::R4, RegState::Kill) 283 .addImm(MaxAlign-1))); 284 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 285 .addReg(ARM::R4, RegState::Kill)); 286 } 287 288 AFI->setShouldRestoreSPFromFP(true); 289 } 290 291 // If we need a base pointer, set it up here. It's whatever the value 292 // of the stack pointer is at this point. Any variable size objects 293 // will be allocated after this, so we can still use the base pointer 294 // to reference locals. 295 // FIXME: Clarify FrameSetup flags here. 296 if (RegInfo->hasBasePointer(MF)) { 297 if (isARM) 298 BuildMI(MBB, MBBI, dl, 299 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 300 .addReg(ARM::SP) 301 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 302 else 303 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 304 RegInfo->getBaseRegister()) 305 .addReg(ARM::SP)); 306 } 307 308 // If the frame has variable sized objects then the epilogue must restore 309 // the sp from fp. We can assume there's an FP here since hasFP already 310 // checks for hasVarSizedObjects. 311 if (MFI->hasVarSizedObjects()) 312 AFI->setShouldRestoreSPFromFP(true); 313} 314 315void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 316 MachineBasicBlock &MBB) const { 317 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 318 assert(MBBI->getDesc().isReturn() && 319 "Can only insert epilog into returning blocks"); 320 unsigned RetOpcode = MBBI->getOpcode(); 321 DebugLoc dl = MBBI->getDebugLoc(); 322 MachineFrameInfo *MFI = MF.getFrameInfo(); 323 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 324 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 325 const ARMBaseInstrInfo &TII = 326 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 327 assert(!AFI->isThumb1OnlyFunction() && 328 "This emitEpilogue does not support Thumb1!"); 329 bool isARM = !AFI->isThumbFunction(); 330 331 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 332 int NumBytes = (int)MFI->getStackSize(); 333 unsigned FramePtr = RegInfo->getFrameRegister(MF); 334 335 // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue. 336 if (MF.getFunction()->getCallingConv() == CallingConv::GHC) 337 return; 338 339 if (!AFI->hasStackFrame()) { 340 if (NumBytes != 0) 341 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 342 } else { 343 // Unwind MBBI to point to first LDR / VLDRD. 344 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); 345 if (MBBI != MBB.begin()) { 346 do 347 --MBBI; 348 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 349 if (!isCSRestore(MBBI, TII, CSRegs)) 350 ++MBBI; 351 } 352 353 // Move SP to start of FP callee save spill area. 354 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 355 AFI->getGPRCalleeSavedArea2Size() + 356 AFI->getDPRCalleeSavedAreaSize()); 357 358 // Reset SP based on frame pointer only if the stack frame extends beyond 359 // frame pointer stack slot or target is ELF and the function has FP. 360 if (AFI->shouldRestoreSPFromFP()) { 361 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 362 if (NumBytes) { 363 if (isARM) 364 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 365 ARMCC::AL, 0, TII); 366 else { 367 // It's not possible to restore SP from FP in a single instruction. 368 // For Darwin, this looks like: 369 // mov sp, r7 370 // sub sp, #24 371 // This is bad, if an interrupt is taken after the mov, sp is in an 372 // inconsistent state. 373 // Use the first callee-saved register as a scratch register. 374 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 375 "No scratch register to restore SP from FP!"); 376 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 377 ARMCC::AL, 0, TII); 378 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 379 ARM::SP) 380 .addReg(ARM::R4)); 381 } 382 } else { 383 // Thumb2 or ARM. 384 if (isARM) 385 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 386 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 387 else 388 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 389 ARM::SP) 390 .addReg(FramePtr)); 391 } 392 } else if (NumBytes) 393 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 394 395 // Increment past our save areas. 396 if (AFI->getDPRCalleeSavedAreaSize()) { 397 MBBI++; 398 // Since vpop register list cannot have gaps, there may be multiple vpop 399 // instructions in the epilogue. 400 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD) 401 MBBI++; 402 } 403 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; 404 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; 405 } 406 407 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || 408 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { 409 // Tail call return: adjust the stack pointer and jump to callee. 410 MBBI = MBB.getLastNonDebugInstr(); 411 MachineOperand &JumpTarget = MBBI->getOperand(0); 412 413 // Jump to label or value in register. 414 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) { 415 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi) 416 ? (STI.isThumb() ? ARM::tTAILJMPd : ARM::TAILJMPd) 417 : (STI.isThumb() ? ARM::tTAILJMPdND : ARM::TAILJMPdND); 418 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 419 if (JumpTarget.isGlobal()) 420 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 421 JumpTarget.getTargetFlags()); 422 else { 423 assert(JumpTarget.isSymbol()); 424 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 425 JumpTarget.getTargetFlags()); 426 } 427 428 // Add the default predicate in Thumb mode. 429 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); 430 } else if (RetOpcode == ARM::TCRETURNri) { 431 BuildMI(MBB, MBBI, dl, 432 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)). 433 addReg(JumpTarget.getReg(), RegState::Kill); 434 } else if (RetOpcode == ARM::TCRETURNriND) { 435 BuildMI(MBB, MBBI, dl, 436 TII.get(STI.isThumb() ? ARM::tTAILJMPrND : ARM::TAILJMPrND)). 437 addReg(JumpTarget.getReg(), RegState::Kill); 438 } 439 440 MachineInstr *NewMI = prior(MBBI); 441 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 442 NewMI->addOperand(MBBI->getOperand(i)); 443 444 // Delete the pseudo instruction TCRETURN. 445 MBB.erase(MBBI); 446 MBBI = NewMI; 447 } 448 449 if (VARegSaveSize) 450 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 451} 452 453/// getFrameIndexReference - Provide a base+offset reference to an FI slot for 454/// debug info. It's the same as what we use for resolving the code-gen 455/// references for now. FIXME: This can go wrong when references are 456/// SP-relative and simple call frames aren't used. 457int 458ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 459 unsigned &FrameReg) const { 460 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 461} 462 463int 464ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, 465 int FI, unsigned &FrameReg, 466 int SPAdj) const { 467 const MachineFrameInfo *MFI = MF.getFrameInfo(); 468 const ARMBaseRegisterInfo *RegInfo = 469 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 470 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 471 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 472 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 473 bool isFixed = MFI->isFixedObjectIndex(FI); 474 475 FrameReg = ARM::SP; 476 Offset += SPAdj; 477 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 478 return Offset - AFI->getGPRCalleeSavedArea1Offset(); 479 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 480 return Offset - AFI->getGPRCalleeSavedArea2Offset(); 481 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 482 return Offset - AFI->getDPRCalleeSavedAreaOffset(); 483 484 // When dynamically realigning the stack, use the frame pointer for 485 // parameters, and the stack/base pointer for locals. 486 if (RegInfo->needsStackRealignment(MF)) { 487 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 488 if (isFixed) { 489 FrameReg = RegInfo->getFrameRegister(MF); 490 Offset = FPOffset; 491 } else if (MFI->hasVarSizedObjects()) { 492 assert(RegInfo->hasBasePointer(MF) && 493 "VLAs and dynamic stack alignment, but missing base pointer!"); 494 FrameReg = RegInfo->getBaseRegister(); 495 } 496 return Offset; 497 } 498 499 // If there is a frame pointer, use it when we can. 500 if (hasFP(MF) && AFI->hasStackFrame()) { 501 // Use frame pointer to reference fixed objects. Use it for locals if 502 // there are VLAs (and thus the SP isn't reliable as a base). 503 if (isFixed || (MFI->hasVarSizedObjects() && 504 !RegInfo->hasBasePointer(MF))) { 505 FrameReg = RegInfo->getFrameRegister(MF); 506 return FPOffset; 507 } else if (MFI->hasVarSizedObjects()) { 508 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); 509 if (AFI->isThumb2Function()) { 510 // Try to use the frame pointer if we can, else use the base pointer 511 // since it's available. This is handy for the emergency spill slot, in 512 // particular. 513 if (FPOffset >= -255 && FPOffset < 0) { 514 FrameReg = RegInfo->getFrameRegister(MF); 515 return FPOffset; 516 } 517 } 518 } else if (AFI->isThumb2Function()) { 519 // Use add <rd>, sp, #<imm8> 520 // ldr <rd>, [sp, #<imm8>] 521 // if at all possible to save space. 522 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) 523 return Offset; 524 // In Thumb2 mode, the negative offset is very limited. Try to avoid 525 // out of range references. ldr <rt>,[<rn>, #-<imm8>] 526 if (FPOffset >= -255 && FPOffset < 0) { 527 FrameReg = RegInfo->getFrameRegister(MF); 528 return FPOffset; 529 } 530 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 531 // Otherwise, use SP or FP, whichever is closer to the stack slot. 532 FrameReg = RegInfo->getFrameRegister(MF); 533 return FPOffset; 534 } 535 } 536 // Use the base pointer if we have one. 537 if (RegInfo->hasBasePointer(MF)) 538 FrameReg = RegInfo->getBaseRegister(); 539 return Offset; 540} 541 542int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, 543 int FI) const { 544 unsigned FrameReg; 545 return getFrameIndexReference(MF, FI, FrameReg); 546} 547 548void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, 549 MachineBasicBlock::iterator MI, 550 const std::vector<CalleeSavedInfo> &CSI, 551 unsigned StmOpc, unsigned StrOpc, 552 bool NoGap, 553 bool(*Func)(unsigned, bool), 554 unsigned MIFlags) const { 555 MachineFunction &MF = *MBB.getParent(); 556 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 557 558 DebugLoc DL; 559 if (MI != MBB.end()) DL = MI->getDebugLoc(); 560 561 SmallVector<std::pair<unsigned,bool>, 4> Regs; 562 unsigned i = CSI.size(); 563 while (i != 0) { 564 unsigned LastReg = 0; 565 for (; i != 0; --i) { 566 unsigned Reg = CSI[i-1].getReg(); 567 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 568 569 // Add the callee-saved register as live-in unless it's LR and 570 // @llvm.returnaddress is called. If LR is returned for 571 // @llvm.returnaddress then it's already added to the function and 572 // entry block live-in sets. 573 bool isKill = true; 574 if (Reg == ARM::LR) { 575 if (MF.getFrameInfo()->isReturnAddressTaken() && 576 MF.getRegInfo().isLiveIn(Reg)) 577 isKill = false; 578 } 579 580 if (isKill) 581 MBB.addLiveIn(Reg); 582 583 // If NoGap is true, push consecutive registers and then leave the rest 584 // for other instructions. e.g. 585 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} 586 if (NoGap && LastReg && LastReg != Reg-1) 587 break; 588 LastReg = Reg; 589 Regs.push_back(std::make_pair(Reg, isKill)); 590 } 591 592 if (Regs.empty()) 593 continue; 594 if (Regs.size() > 1 || StrOpc== 0) { 595 MachineInstrBuilder MIB = 596 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) 597 .addReg(ARM::SP).setMIFlags(MIFlags)); 598 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 599 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 600 } else if (Regs.size() == 1) { 601 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), 602 ARM::SP) 603 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) 604 .addReg(ARM::SP).setMIFlags(MIFlags) 605 .addImm(-4); 606 AddDefaultPred(MIB); 607 } 608 Regs.clear(); 609 } 610} 611 612void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, 613 MachineBasicBlock::iterator MI, 614 const std::vector<CalleeSavedInfo> &CSI, 615 unsigned LdmOpc, unsigned LdrOpc, 616 bool isVarArg, bool NoGap, 617 bool(*Func)(unsigned, bool)) const { 618 MachineFunction &MF = *MBB.getParent(); 619 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 620 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 621 DebugLoc DL = MI->getDebugLoc(); 622 unsigned RetOpcode = MI->getOpcode(); 623 bool isTailCall = (RetOpcode == ARM::TCRETURNdi || 624 RetOpcode == ARM::TCRETURNdiND || 625 RetOpcode == ARM::TCRETURNri || 626 RetOpcode == ARM::TCRETURNriND); 627 628 SmallVector<unsigned, 4> Regs; 629 unsigned i = CSI.size(); 630 while (i != 0) { 631 unsigned LastReg = 0; 632 bool DeleteRet = false; 633 for (; i != 0; --i) { 634 unsigned Reg = CSI[i-1].getReg(); 635 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 636 637 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) { 638 Reg = ARM::PC; 639 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; 640 // Fold the return instruction into the LDM. 641 DeleteRet = true; 642 } 643 644 // If NoGap is true, pop consecutive registers and then leave the rest 645 // for other instructions. e.g. 646 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} 647 if (NoGap && LastReg && LastReg != Reg-1) 648 break; 649 650 LastReg = Reg; 651 Regs.push_back(Reg); 652 } 653 654 if (Regs.empty()) 655 continue; 656 if (Regs.size() > 1 || LdrOpc == 0) { 657 MachineInstrBuilder MIB = 658 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) 659 .addReg(ARM::SP)); 660 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 661 MIB.addReg(Regs[i], getDefRegState(true)); 662 if (DeleteRet) { 663 MIB->copyImplicitOps(&*MI); 664 MI->eraseFromParent(); 665 } 666 MI = MIB; 667 } else if (Regs.size() == 1) { 668 // If we adjusted the reg to PC from LR above, switch it back here. We 669 // only do that for LDM. 670 if (Regs[0] == ARM::PC) 671 Regs[0] = ARM::LR; 672 MachineInstrBuilder MIB = 673 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) 674 .addReg(ARM::SP, RegState::Define) 675 .addReg(ARM::SP); 676 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 677 // that refactoring is complete (eventually). 678 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { 679 MIB.addReg(0); 680 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); 681 } else 682 MIB.addImm(4); 683 AddDefaultPred(MIB); 684 } 685 Regs.clear(); 686 } 687} 688 689bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 690 MachineBasicBlock::iterator MI, 691 const std::vector<CalleeSavedInfo> &CSI, 692 const TargetRegisterInfo *TRI) const { 693 if (CSI.empty()) 694 return false; 695 696 MachineFunction &MF = *MBB.getParent(); 697 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 698 699 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; 700 unsigned PushOneOpc = AFI->isThumbFunction() ? 701 ARM::t2STR_PRE : ARM::STR_PRE_IMM; 702 unsigned FltOpc = ARM::VSTMDDB_UPD; 703 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 704 MachineInstr::FrameSetup); 705 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 706 MachineInstr::FrameSetup); 707 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register, 708 MachineInstr::FrameSetup); 709 710 return true; 711} 712 713bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 714 MachineBasicBlock::iterator MI, 715 const std::vector<CalleeSavedInfo> &CSI, 716 const TargetRegisterInfo *TRI) const { 717 if (CSI.empty()) 718 return false; 719 720 MachineFunction &MF = *MBB.getParent(); 721 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 722 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 723 724 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 725 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; 726 unsigned FltOpc = ARM::VLDMDIA_UPD; 727 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register); 728 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 729 &isARMArea2Register); 730 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 731 &isARMArea1Register); 732 733 return true; 734} 735 736// FIXME: Make generic? 737static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 738 const ARMBaseInstrInfo &TII) { 739 unsigned FnSize = 0; 740 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 741 MBBI != E; ++MBBI) { 742 const MachineBasicBlock &MBB = *MBBI; 743 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 744 I != E; ++I) 745 FnSize += TII.GetInstSizeInBytes(I); 746 } 747 return FnSize; 748} 749 750/// estimateStackSize - Estimate and return the size of the frame. 751/// FIXME: Make generic? 752static unsigned estimateStackSize(MachineFunction &MF) { 753 const MachineFrameInfo *MFI = MF.getFrameInfo(); 754 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 755 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 756 unsigned MaxAlign = MFI->getMaxAlignment(); 757 int Offset = 0; 758 759 // This code is very, very similar to PEI::calculateFrameObjectOffsets(). 760 // It really should be refactored to share code. Until then, changes 761 // should keep in mind that there's tight coupling between the two. 762 763 for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) { 764 int FixedOff = -MFI->getObjectOffset(i); 765 if (FixedOff > Offset) Offset = FixedOff; 766 } 767 for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { 768 if (MFI->isDeadObjectIndex(i)) 769 continue; 770 Offset += MFI->getObjectSize(i); 771 unsigned Align = MFI->getObjectAlignment(i); 772 // Adjust to alignment boundary 773 Offset = (Offset+Align-1)/Align*Align; 774 775 MaxAlign = std::max(Align, MaxAlign); 776 } 777 778 if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF)) 779 Offset += MFI->getMaxCallFrameSize(); 780 781 // Round up the size to a multiple of the alignment. If the function has 782 // any calls or alloca's, align to the target's StackAlignment value to 783 // ensure that the callee's frame or the alloca data is suitably aligned; 784 // otherwise, for leaf functions, align to the TransientStackAlignment 785 // value. 786 unsigned StackAlign; 787 if (MFI->adjustsStack() || MFI->hasVarSizedObjects() || 788 (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0)) 789 StackAlign = TFI->getStackAlignment(); 790 else 791 StackAlign = TFI->getTransientStackAlignment(); 792 793 // If the frame pointer is eliminated, all frame offsets will be relative to 794 // SP not FP. Align to MaxAlign so this works. 795 StackAlign = std::max(StackAlign, MaxAlign); 796 unsigned AlignMask = StackAlign - 1; 797 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask); 798 799 return (unsigned)Offset; 800} 801 802/// estimateRSStackSizeLimit - Look at each instruction that references stack 803/// frames and return the stack size limit beyond which some of these 804/// instructions will require a scratch register during their expansion later. 805// FIXME: Move to TII? 806static unsigned estimateRSStackSizeLimit(MachineFunction &MF, 807 const TargetFrameLowering *TFI) { 808 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 809 unsigned Limit = (1 << 12) - 1; 810 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 811 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 812 I != E; ++I) { 813 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 814 if (!I->getOperand(i).isFI()) continue; 815 816 // When using ADDri to get the address of a stack object, 255 is the 817 // largest offset guaranteed to fit in the immediate offset. 818 if (I->getOpcode() == ARM::ADDri) { 819 Limit = std::min(Limit, (1U << 8) - 1); 820 break; 821 } 822 823 // Otherwise check the addressing mode. 824 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 825 case ARMII::AddrMode3: 826 case ARMII::AddrModeT2_i8: 827 Limit = std::min(Limit, (1U << 8) - 1); 828 break; 829 case ARMII::AddrMode5: 830 case ARMII::AddrModeT2_i8s4: 831 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 832 break; 833 case ARMII::AddrModeT2_i12: 834 // i12 supports only positive offset so these will be converted to 835 // i8 opcodes. See llvm::rewriteT2FrameIndex. 836 if (TFI->hasFP(MF) && AFI->hasStackFrame()) 837 Limit = std::min(Limit, (1U << 8) - 1); 838 break; 839 case ARMII::AddrMode4: 840 case ARMII::AddrMode6: 841 // Addressing modes 4 & 6 (load/store) instructions can't encode an 842 // immediate offset for stack references. 843 return 0; 844 default: 845 break; 846 } 847 break; // At most one FI per instruction 848 } 849 } 850 } 851 852 return Limit; 853} 854 855void 856ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 857 RegScavenger *RS) const { 858 // This tells PEI to spill the FP as if it is any other callee-save register 859 // to take advantage the eliminateFrameIndex machinery. This also ensures it 860 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 861 // to combine multiple loads / stores. 862 bool CanEliminateFrame = true; 863 bool CS1Spilled = false; 864 bool LRSpilled = false; 865 unsigned NumGPRSpills = 0; 866 SmallVector<unsigned, 4> UnspilledCS1GPRs; 867 SmallVector<unsigned, 4> UnspilledCS2GPRs; 868 const ARMBaseRegisterInfo *RegInfo = 869 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 870 const ARMBaseInstrInfo &TII = 871 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 872 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 873 MachineFrameInfo *MFI = MF.getFrameInfo(); 874 unsigned FramePtr = RegInfo->getFrameRegister(MF); 875 876 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 877 // scratch register. Also spill R4 if Thumb2 function has varsized objects, 878 // since it's not always possible to restore sp from fp in a single 879 // instruction. 880 // FIXME: It will be better just to find spare register here. 881 if (AFI->isThumb2Function() && 882 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) 883 MF.getRegInfo().setPhysRegUsed(ARM::R4); 884 885 if (AFI->isThumb1OnlyFunction()) { 886 // Spill LR if Thumb1 function uses variable length argument lists. 887 if (AFI->getVarArgsRegSaveSize() > 0) 888 MF.getRegInfo().setPhysRegUsed(ARM::LR); 889 890 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know 891 // for sure what the stack size will be, but for this, an estimate is good 892 // enough. If there anything changes it, it'll be a spill, which implies 893 // we've used all the registers and so R4 is already used, so not marking 894 // it here will be OK. 895 // FIXME: It will be better just to find spare register here. 896 unsigned StackSize = estimateStackSize(MF); 897 if (MFI->hasVarSizedObjects() || StackSize > 508) 898 MF.getRegInfo().setPhysRegUsed(ARM::R4); 899 } 900 901 // Spill the BasePtr if it's used. 902 if (RegInfo->hasBasePointer(MF)) 903 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); 904 905 // Don't spill FP if the frame can be eliminated. This is determined 906 // by scanning the callee-save registers to see if any is used. 907 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); 908 for (unsigned i = 0; CSRegs[i]; ++i) { 909 unsigned Reg = CSRegs[i]; 910 bool Spilled = false; 911 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 912 Spilled = true; 913 CanEliminateFrame = false; 914 } else { 915 // Check alias registers too. 916 for (const unsigned *Aliases = 917 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) { 918 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 919 Spilled = true; 920 CanEliminateFrame = false; 921 } 922 } 923 } 924 925 if (!ARM::GPRRegisterClass->contains(Reg)) 926 continue; 927 928 if (Spilled) { 929 NumGPRSpills++; 930 931 if (!STI.isTargetDarwin()) { 932 if (Reg == ARM::LR) 933 LRSpilled = true; 934 CS1Spilled = true; 935 continue; 936 } 937 938 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 939 switch (Reg) { 940 case ARM::LR: 941 LRSpilled = true; 942 // Fallthrough 943 case ARM::R4: case ARM::R5: 944 case ARM::R6: case ARM::R7: 945 CS1Spilled = true; 946 break; 947 default: 948 break; 949 } 950 } else { 951 if (!STI.isTargetDarwin()) { 952 UnspilledCS1GPRs.push_back(Reg); 953 continue; 954 } 955 956 switch (Reg) { 957 case ARM::R4: case ARM::R5: 958 case ARM::R6: case ARM::R7: 959 case ARM::LR: 960 UnspilledCS1GPRs.push_back(Reg); 961 break; 962 default: 963 UnspilledCS2GPRs.push_back(Reg); 964 break; 965 } 966 } 967 } 968 969 bool ForceLRSpill = false; 970 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 971 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 972 // Force LR to be spilled if the Thumb function size is > 2048. This enables 973 // use of BL to implement far jump. If it turns out that it's not needed 974 // then the branch fix up path will undo it. 975 if (FnSize >= (1 << 11)) { 976 CanEliminateFrame = false; 977 ForceLRSpill = true; 978 } 979 } 980 981 // If any of the stack slot references may be out of range of an immediate 982 // offset, make sure a register (or a spill slot) is available for the 983 // register scavenger. Note that if we're indexing off the frame pointer, the 984 // effective stack size is 4 bytes larger since the FP points to the stack 985 // slot of the previous FP. Also, if we have variable sized objects in the 986 // function, stack slot references will often be negative, and some of 987 // our instructions are positive-offset only, so conservatively consider 988 // that case to want a spill slot (or register) as well. Similarly, if 989 // the function adjusts the stack pointer during execution and the 990 // adjustments aren't already part of our stack size estimate, our offset 991 // calculations may be off, so be conservative. 992 // FIXME: We could add logic to be more precise about negative offsets 993 // and which instructions will need a scratch register for them. Is it 994 // worth the effort and added fragility? 995 bool BigStack = 996 (RS && 997 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= 998 estimateRSStackSizeLimit(MF, this))) 999 || MFI->hasVarSizedObjects() 1000 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 1001 1002 bool ExtraCSSpill = false; 1003 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { 1004 AFI->setHasStackFrame(true); 1005 1006 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 1007 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1008 if (!LRSpilled && CS1Spilled) { 1009 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1010 NumGPRSpills++; 1011 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1012 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1013 ForceLRSpill = false; 1014 ExtraCSSpill = true; 1015 } 1016 1017 if (hasFP(MF)) { 1018 MF.getRegInfo().setPhysRegUsed(FramePtr); 1019 NumGPRSpills++; 1020 } 1021 1022 // If stack and double are 8-byte aligned and we are spilling an odd number 1023 // of GPRs, spill one extra callee save GPR so we won't have to pad between 1024 // the integer and double callee save areas. 1025 unsigned TargetAlign = getStackAlignment(); 1026 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1027 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1028 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1029 unsigned Reg = UnspilledCS1GPRs[i]; 1030 // Don't spill high register if the function is thumb1 1031 if (!AFI->isThumb1OnlyFunction() || 1032 isARMLowRegister(Reg) || Reg == ARM::LR) { 1033 MF.getRegInfo().setPhysRegUsed(Reg); 1034 if (!RegInfo->isReservedReg(MF, Reg)) 1035 ExtraCSSpill = true; 1036 break; 1037 } 1038 } 1039 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { 1040 unsigned Reg = UnspilledCS2GPRs.front(); 1041 MF.getRegInfo().setPhysRegUsed(Reg); 1042 if (!RegInfo->isReservedReg(MF, Reg)) 1043 ExtraCSSpill = true; 1044 } 1045 } 1046 1047 // Estimate if we might need to scavenge a register at some point in order 1048 // to materialize a stack offset. If so, either spill one additional 1049 // callee-saved register or reserve a special spill slot to facilitate 1050 // register scavenging. Thumb1 needs a spill slot for stack pointer 1051 // adjustments also, even when the frame itself is small. 1052 if (BigStack && !ExtraCSSpill) { 1053 // If any non-reserved CS register isn't spilled, just spill one or two 1054 // extra. That should take care of it! 1055 unsigned NumExtras = TargetAlign / 4; 1056 SmallVector<unsigned, 2> Extras; 1057 while (NumExtras && !UnspilledCS1GPRs.empty()) { 1058 unsigned Reg = UnspilledCS1GPRs.back(); 1059 UnspilledCS1GPRs.pop_back(); 1060 if (!RegInfo->isReservedReg(MF, Reg) && 1061 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 1062 Reg == ARM::LR)) { 1063 Extras.push_back(Reg); 1064 NumExtras--; 1065 } 1066 } 1067 // For non-Thumb1 functions, also check for hi-reg CS registers 1068 if (!AFI->isThumb1OnlyFunction()) { 1069 while (NumExtras && !UnspilledCS2GPRs.empty()) { 1070 unsigned Reg = UnspilledCS2GPRs.back(); 1071 UnspilledCS2GPRs.pop_back(); 1072 if (!RegInfo->isReservedReg(MF, Reg)) { 1073 Extras.push_back(Reg); 1074 NumExtras--; 1075 } 1076 } 1077 } 1078 if (Extras.size() && NumExtras == 0) { 1079 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1080 MF.getRegInfo().setPhysRegUsed(Extras[i]); 1081 } 1082 } else if (!AFI->isThumb1OnlyFunction()) { 1083 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 1084 // closest to SP or frame pointer. 1085 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 1086 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1087 RC->getAlignment(), 1088 false)); 1089 } 1090 } 1091 } 1092 1093 if (ForceLRSpill) { 1094 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1095 AFI->setLRIsSpilledForFarJump(true); 1096 } 1097} 1098