1//===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CellSPU-specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SPUSubtarget.h"
15#include "SPU.h"
16#include "SPURegisterInfo.h"
17#include "llvm/Support/TargetRegistry.h"
18#include "llvm/ADT/SmallVector.h"
19
20#define GET_SUBTARGETINFO_TARGET_DESC
21#define GET_SUBTARGETINFO_CTOR
22#include "SPUGenSubtargetInfo.inc"
23
24using namespace llvm;
25
26SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
27                           const std::string &FS) :
28  SPUGenSubtargetInfo(TT, CPU, FS),
29  StackAlignment(16),
30  ProcDirective(SPU::DEFAULT_PROC),
31  UseLargeMem(false)
32{
33  // Should be the target SPU processor type. For now, since there's only
34  // one, simply default to the current "v0" default:
35  std::string default_cpu("v0");
36
37  // Parse features string.
38  ParseSubtargetFeatures(default_cpu, FS);
39
40  // Initialize scheduling itinerary for the specified CPU.
41  InstrItins = getInstrItineraryForCPU(default_cpu);
42}
43
44/// SetJITMode - This is called to inform the subtarget info that we are
45/// producing code for the JIT.
46void SPUSubtarget::SetJITMode() {
47}
48
49/// Enable PostRA scheduling for optimization levels -O2 and -O3.
50bool SPUSubtarget::enablePostRAScheduler(
51                       CodeGenOpt::Level OptLevel,
52                       TargetSubtargetInfo::AntiDepBreakMode& Mode,
53                       RegClassVector& CriticalPathRCs) const {
54  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
55  // CriticalPathsRCs seems to be the set of
56  // RegisterClasses that antidep breakings are performed for.
57  // Do it for all register classes
58  CriticalPathRCs.clear();
59  CriticalPathRCs.push_back(&SPU::R8CRegClass);
60  CriticalPathRCs.push_back(&SPU::R16CRegClass);
61  CriticalPathRCs.push_back(&SPU::R32CRegClass);
62  CriticalPathRCs.push_back(&SPU::R32FPRegClass);
63  CriticalPathRCs.push_back(&SPU::R64CRegClass);
64  CriticalPathRCs.push_back(&SPU::VECREGRegClass);
65  return OptLevel >= CodeGenOpt::Default;
66}
67