1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  setStackPointerRegisterToSaveRestore(MSP430::SPW);
81  setBooleanContents(ZeroOrOneBooleanContent);
82  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
83  setSchedulingPreference(Sched::Latency);
84
85  // We have post-incremented loads / stores.
86  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
87  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
88
89  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
90  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
91  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
92  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
93  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
94
95  // We don't have any truncstores
96  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
97
98  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
99  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
100  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
101  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
102  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
103  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
104  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
105  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
106  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
107  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
108  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
109  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
110  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
111  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
112  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
113  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
114  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
115  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
116  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
117  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
118  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
119  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
120  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
121  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
122  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
123  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
124
125  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
126  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
128  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
129  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
130  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
131
132  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
133  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
134  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
135  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
136  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
137  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
138
139  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
140
141  // FIXME: Implement efficiently multiplication by a constant
142  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
143  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
144  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
145  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
146  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
147  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
148  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
149  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
150  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
151  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
152
153  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
154  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
155  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
156  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
157  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
158  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
159  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
160  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
161  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
162  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
163  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
164  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
165
166  // Libcalls names.
167  if (HWMultMode == HWMultIntr) {
168    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
169    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
170  } else if (HWMultMode == HWMultNoIntr) {
171    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
172    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
173  }
174
175  setMinFunctionAlignment(1);
176  setPrefFunctionAlignment(2);
177}
178
179SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
180                                             SelectionDAG &DAG) const {
181  switch (Op.getOpcode()) {
182  case ISD::SHL: // FALLTHROUGH
183  case ISD::SRL:
184  case ISD::SRA:              return LowerShifts(Op, DAG);
185  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
186  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
187  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
188  case ISD::SETCC:            return LowerSETCC(Op, DAG);
189  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
190  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
191  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
192  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
193  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
194  default:
195    llvm_unreachable("unimplemented operand");
196    return SDValue();
197  }
198}
199
200//===----------------------------------------------------------------------===//
201//                       MSP430 Inline Assembly Support
202//===----------------------------------------------------------------------===//
203
204/// getConstraintType - Given a constraint letter, return the type of
205/// constraint it is for this target.
206TargetLowering::ConstraintType
207MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
208  if (Constraint.size() == 1) {
209    switch (Constraint[0]) {
210    case 'r':
211      return C_RegisterClass;
212    default:
213      break;
214    }
215  }
216  return TargetLowering::getConstraintType(Constraint);
217}
218
219std::pair<unsigned, const TargetRegisterClass*>
220MSP430TargetLowering::
221getRegForInlineAsmConstraint(const std::string &Constraint,
222                             EVT VT) const {
223  if (Constraint.size() == 1) {
224    // GCC Constraint Letters
225    switch (Constraint[0]) {
226    default: break;
227    case 'r':   // GENERAL_REGS
228      if (VT == MVT::i8)
229        return std::make_pair(0U, MSP430::GR8RegisterClass);
230
231      return std::make_pair(0U, MSP430::GR16RegisterClass);
232    }
233  }
234
235  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
236}
237
238//===----------------------------------------------------------------------===//
239//                      Calling Convention Implementation
240//===----------------------------------------------------------------------===//
241
242#include "MSP430GenCallingConv.inc"
243
244SDValue
245MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
246                                           CallingConv::ID CallConv,
247                                           bool isVarArg,
248                                           const SmallVectorImpl<ISD::InputArg>
249                                             &Ins,
250                                           DebugLoc dl,
251                                           SelectionDAG &DAG,
252                                           SmallVectorImpl<SDValue> &InVals)
253                                             const {
254
255  switch (CallConv) {
256  default:
257    llvm_unreachable("Unsupported calling convention");
258  case CallingConv::C:
259  case CallingConv::Fast:
260    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
261  case CallingConv::MSP430_INTR:
262   if (Ins.empty())
263     return Chain;
264   else {
265    report_fatal_error("ISRs cannot have arguments");
266    return SDValue();
267   }
268  }
269}
270
271SDValue
272MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
273                                CallingConv::ID CallConv, bool isVarArg,
274                                bool &isTailCall,
275                                const SmallVectorImpl<ISD::OutputArg> &Outs,
276                                const SmallVectorImpl<SDValue> &OutVals,
277                                const SmallVectorImpl<ISD::InputArg> &Ins,
278                                DebugLoc dl, SelectionDAG &DAG,
279                                SmallVectorImpl<SDValue> &InVals) const {
280  // MSP430 target does not yet support tail call optimization.
281  isTailCall = false;
282
283  switch (CallConv) {
284  default:
285    llvm_unreachable("Unsupported calling convention");
286  case CallingConv::Fast:
287  case CallingConv::C:
288    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
289                          Outs, OutVals, Ins, dl, DAG, InVals);
290  case CallingConv::MSP430_INTR:
291    report_fatal_error("ISRs cannot be called directly");
292    return SDValue();
293  }
294}
295
296/// LowerCCCArguments - transform physical registers into virtual registers and
297/// generate load operations for arguments places on the stack.
298// FIXME: struct return stuff
299// FIXME: varargs
300SDValue
301MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
302                                        CallingConv::ID CallConv,
303                                        bool isVarArg,
304                                        const SmallVectorImpl<ISD::InputArg>
305                                          &Ins,
306                                        DebugLoc dl,
307                                        SelectionDAG &DAG,
308                                        SmallVectorImpl<SDValue> &InVals)
309                                          const {
310  MachineFunction &MF = DAG.getMachineFunction();
311  MachineFrameInfo *MFI = MF.getFrameInfo();
312  MachineRegisterInfo &RegInfo = MF.getRegInfo();
313
314  // Assign locations to all of the incoming arguments.
315  SmallVector<CCValAssign, 16> ArgLocs;
316  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
317		 getTargetMachine(), ArgLocs, *DAG.getContext());
318  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
319
320  assert(!isVarArg && "Varargs not supported yet");
321
322  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
323    CCValAssign &VA = ArgLocs[i];
324    if (VA.isRegLoc()) {
325      // Arguments passed in registers
326      EVT RegVT = VA.getLocVT();
327      switch (RegVT.getSimpleVT().SimpleTy) {
328      default:
329        {
330#ifndef NDEBUG
331          errs() << "LowerFormalArguments Unhandled argument type: "
332               << RegVT.getSimpleVT().SimpleTy << "\n";
333#endif
334          llvm_unreachable(0);
335        }
336      case MVT::i16:
337        unsigned VReg =
338          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
339        RegInfo.addLiveIn(VA.getLocReg(), VReg);
340        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
341
342        // If this is an 8-bit value, it is really passed promoted to 16
343        // bits. Insert an assert[sz]ext to capture this, then truncate to the
344        // right size.
345        if (VA.getLocInfo() == CCValAssign::SExt)
346          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
347                                 DAG.getValueType(VA.getValVT()));
348        else if (VA.getLocInfo() == CCValAssign::ZExt)
349          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
350                                 DAG.getValueType(VA.getValVT()));
351
352        if (VA.getLocInfo() != CCValAssign::Full)
353          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
354
355        InVals.push_back(ArgValue);
356      }
357    } else {
358      // Sanity check
359      assert(VA.isMemLoc());
360      // Load the argument to a virtual register
361      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
362      if (ObjSize > 2) {
363        errs() << "LowerFormalArguments Unhandled argument type: "
364             << EVT(VA.getLocVT()).getEVTString()
365             << "\n";
366      }
367      // Create the frame index object for this incoming parameter...
368      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
369
370      // Create the SelectionDAG nodes corresponding to a load
371      //from this parameter
372      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
373      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
374                                   MachinePointerInfo::getFixedStack(FI),
375                                   false, false, 0));
376    }
377  }
378
379  return Chain;
380}
381
382SDValue
383MSP430TargetLowering::LowerReturn(SDValue Chain,
384                                  CallingConv::ID CallConv, bool isVarArg,
385                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
386                                  const SmallVectorImpl<SDValue> &OutVals,
387                                  DebugLoc dl, SelectionDAG &DAG) const {
388
389  // CCValAssign - represent the assignment of the return value to a location
390  SmallVector<CCValAssign, 16> RVLocs;
391
392  // ISRs cannot return any value.
393  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
394    report_fatal_error("ISRs cannot return any value");
395    return SDValue();
396  }
397
398  // CCState - Info about the registers and stack slot.
399  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
400		 getTargetMachine(), RVLocs, *DAG.getContext());
401
402  // Analize return values.
403  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
404
405  // If this is the first return lowered for this function, add the regs to the
406  // liveout set for the function.
407  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
408    for (unsigned i = 0; i != RVLocs.size(); ++i)
409      if (RVLocs[i].isRegLoc())
410        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
411  }
412
413  SDValue Flag;
414
415  // Copy the result values into the output registers.
416  for (unsigned i = 0; i != RVLocs.size(); ++i) {
417    CCValAssign &VA = RVLocs[i];
418    assert(VA.isRegLoc() && "Can only return in registers!");
419
420    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
421                             OutVals[i], Flag);
422
423    // Guarantee that all emitted copies are stuck together,
424    // avoiding something bad.
425    Flag = Chain.getValue(1);
426  }
427
428  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
429                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
430
431  if (Flag.getNode())
432    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
433
434  // Return Void
435  return DAG.getNode(Opc, dl, MVT::Other, Chain);
436}
437
438/// LowerCCCCallTo - functions arguments are copied from virtual regs to
439/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
440/// TODO: sret.
441SDValue
442MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
443                                     CallingConv::ID CallConv, bool isVarArg,
444                                     bool isTailCall,
445                                     const SmallVectorImpl<ISD::OutputArg>
446                                       &Outs,
447                                     const SmallVectorImpl<SDValue> &OutVals,
448                                     const SmallVectorImpl<ISD::InputArg> &Ins,
449                                     DebugLoc dl, SelectionDAG &DAG,
450                                     SmallVectorImpl<SDValue> &InVals) const {
451  // Analyze operands of the call, assigning locations to each operand.
452  SmallVector<CCValAssign, 16> ArgLocs;
453  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
454		 getTargetMachine(), ArgLocs, *DAG.getContext());
455
456  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
457
458  // Get a count of how many bytes are to be pushed on the stack.
459  unsigned NumBytes = CCInfo.getNextStackOffset();
460
461  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
462                                                      getPointerTy(), true));
463
464  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
465  SmallVector<SDValue, 12> MemOpChains;
466  SDValue StackPtr;
467
468  // Walk the register/memloc assignments, inserting copies/loads.
469  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
470    CCValAssign &VA = ArgLocs[i];
471
472    SDValue Arg = OutVals[i];
473
474    // Promote the value if needed.
475    switch (VA.getLocInfo()) {
476      default: llvm_unreachable("Unknown loc info!");
477      case CCValAssign::Full: break;
478      case CCValAssign::SExt:
479        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
480        break;
481      case CCValAssign::ZExt:
482        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
483        break;
484      case CCValAssign::AExt:
485        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
486        break;
487    }
488
489    // Arguments that can be passed on register must be kept at RegsToPass
490    // vector
491    if (VA.isRegLoc()) {
492      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
493    } else {
494      assert(VA.isMemLoc());
495
496      if (StackPtr.getNode() == 0)
497        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
498
499      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
500                                   StackPtr,
501                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
502
503
504      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
505                                         MachinePointerInfo(),false, false, 0));
506    }
507  }
508
509  // Transform all store nodes into one single node because all store nodes are
510  // independent of each other.
511  if (!MemOpChains.empty())
512    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
513                        &MemOpChains[0], MemOpChains.size());
514
515  // Build a sequence of copy-to-reg nodes chained together with token chain and
516  // flag operands which copy the outgoing args into registers.  The InFlag in
517  // necessary since all emitted instructions must be stuck together.
518  SDValue InFlag;
519  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
520    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
521                             RegsToPass[i].second, InFlag);
522    InFlag = Chain.getValue(1);
523  }
524
525  // If the callee is a GlobalAddress node (quite common, every direct call is)
526  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
527  // Likewise ExternalSymbol -> TargetExternalSymbol.
528  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
529    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
530  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
531    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
532
533  // Returns a chain & a flag for retval copy to use.
534  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
535  SmallVector<SDValue, 8> Ops;
536  Ops.push_back(Chain);
537  Ops.push_back(Callee);
538
539  // Add argument registers to the end of the list so that they are
540  // known live into the call.
541  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
542    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
543                                  RegsToPass[i].second.getValueType()));
544
545  if (InFlag.getNode())
546    Ops.push_back(InFlag);
547
548  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
549  InFlag = Chain.getValue(1);
550
551  // Create the CALLSEQ_END node.
552  Chain = DAG.getCALLSEQ_END(Chain,
553                             DAG.getConstant(NumBytes, getPointerTy(), true),
554                             DAG.getConstant(0, getPointerTy(), true),
555                             InFlag);
556  InFlag = Chain.getValue(1);
557
558  // Handle result values, copying them out of physregs into vregs that we
559  // return.
560  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
561                         DAG, InVals);
562}
563
564/// LowerCallResult - Lower the result values of a call into the
565/// appropriate copies out of appropriate physical registers.
566///
567SDValue
568MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
569                                      CallingConv::ID CallConv, bool isVarArg,
570                                      const SmallVectorImpl<ISD::InputArg> &Ins,
571                                      DebugLoc dl, SelectionDAG &DAG,
572                                      SmallVectorImpl<SDValue> &InVals) const {
573
574  // Assign locations to each value returned by this call.
575  SmallVector<CCValAssign, 16> RVLocs;
576  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
577		 getTargetMachine(), RVLocs, *DAG.getContext());
578
579  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
580
581  // Copy all of the result registers out of their specified physreg.
582  for (unsigned i = 0; i != RVLocs.size(); ++i) {
583    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
584                               RVLocs[i].getValVT(), InFlag).getValue(1);
585    InFlag = Chain.getValue(2);
586    InVals.push_back(Chain.getValue(0));
587  }
588
589  return Chain;
590}
591
592SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
593                                          SelectionDAG &DAG) const {
594  unsigned Opc = Op.getOpcode();
595  SDNode* N = Op.getNode();
596  EVT VT = Op.getValueType();
597  DebugLoc dl = N->getDebugLoc();
598
599  // Expand non-constant shifts to loops:
600  if (!isa<ConstantSDNode>(N->getOperand(1)))
601    switch (Opc) {
602    default:
603      assert(0 && "Invalid shift opcode!");
604    case ISD::SHL:
605      return DAG.getNode(MSP430ISD::SHL, dl,
606                         VT, N->getOperand(0), N->getOperand(1));
607    case ISD::SRA:
608      return DAG.getNode(MSP430ISD::SRA, dl,
609                         VT, N->getOperand(0), N->getOperand(1));
610    case ISD::SRL:
611      return DAG.getNode(MSP430ISD::SRL, dl,
612                         VT, N->getOperand(0), N->getOperand(1));
613    }
614
615  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
616
617  // Expand the stuff into sequence of shifts.
618  // FIXME: for some shift amounts this might be done better!
619  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
620  SDValue Victim = N->getOperand(0);
621
622  if (Opc == ISD::SRL && ShiftAmount) {
623    // Emit a special goodness here:
624    // srl A, 1 => clrc; rrc A
625    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
626    ShiftAmount -= 1;
627  }
628
629  while (ShiftAmount--)
630    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
631                         dl, VT, Victim);
632
633  return Victim;
634}
635
636SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
637                                                 SelectionDAG &DAG) const {
638  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
639  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
640
641  // Create the TargetGlobalAddress node, folding in the constant offset.
642  SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
643                                              getPointerTy(), Offset);
644  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
645                     getPointerTy(), Result);
646}
647
648SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
649                                                  SelectionDAG &DAG) const {
650  DebugLoc dl = Op.getDebugLoc();
651  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
652  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
653
654  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
655}
656
657SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
658                                                SelectionDAG &DAG) const {
659  DebugLoc dl = Op.getDebugLoc();
660  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
661  SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
662
663  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
664}
665
666static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
667                       ISD::CondCode CC,
668                       DebugLoc dl, SelectionDAG &DAG) {
669  // FIXME: Handle bittests someday
670  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
671
672  // FIXME: Handle jump negative someday
673  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
674  switch (CC) {
675  default: llvm_unreachable("Invalid integer condition!");
676  case ISD::SETEQ:
677    TCC = MSP430CC::COND_E;     // aka COND_Z
678    // Minor optimization: if LHS is a constant, swap operands, then the
679    // constant can be folded into comparison.
680    if (LHS.getOpcode() == ISD::Constant)
681      std::swap(LHS, RHS);
682    break;
683  case ISD::SETNE:
684    TCC = MSP430CC::COND_NE;    // aka COND_NZ
685    // Minor optimization: if LHS is a constant, swap operands, then the
686    // constant can be folded into comparison.
687    if (LHS.getOpcode() == ISD::Constant)
688      std::swap(LHS, RHS);
689    break;
690  case ISD::SETULE:
691    std::swap(LHS, RHS);        // FALLTHROUGH
692  case ISD::SETUGE:
693    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
694    // fold constant into instruction.
695    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
696      LHS = RHS;
697      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
698      TCC = MSP430CC::COND_LO;
699      break;
700    }
701    TCC = MSP430CC::COND_HS;    // aka COND_C
702    break;
703  case ISD::SETUGT:
704    std::swap(LHS, RHS);        // FALLTHROUGH
705  case ISD::SETULT:
706    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
707    // fold constant into instruction.
708    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
709      LHS = RHS;
710      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
711      TCC = MSP430CC::COND_HS;
712      break;
713    }
714    TCC = MSP430CC::COND_LO;    // aka COND_NC
715    break;
716  case ISD::SETLE:
717    std::swap(LHS, RHS);        // FALLTHROUGH
718  case ISD::SETGE:
719    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
720    // fold constant into instruction.
721    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
722      LHS = RHS;
723      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
724      TCC = MSP430CC::COND_L;
725      break;
726    }
727    TCC = MSP430CC::COND_GE;
728    break;
729  case ISD::SETGT:
730    std::swap(LHS, RHS);        // FALLTHROUGH
731  case ISD::SETLT:
732    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
733    // fold constant into instruction.
734    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
735      LHS = RHS;
736      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
737      TCC = MSP430CC::COND_GE;
738      break;
739    }
740    TCC = MSP430CC::COND_L;
741    break;
742  }
743
744  TargetCC = DAG.getConstant(TCC, MVT::i8);
745  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
746}
747
748
749SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
750  SDValue Chain = Op.getOperand(0);
751  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
752  SDValue LHS   = Op.getOperand(2);
753  SDValue RHS   = Op.getOperand(3);
754  SDValue Dest  = Op.getOperand(4);
755  DebugLoc dl   = Op.getDebugLoc();
756
757  SDValue TargetCC;
758  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
759
760  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
761                     Chain, Dest, TargetCC, Flag);
762}
763
764SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
765  SDValue LHS   = Op.getOperand(0);
766  SDValue RHS   = Op.getOperand(1);
767  DebugLoc dl   = Op.getDebugLoc();
768
769  // If we are doing an AND and testing against zero, then the CMP
770  // will not be generated.  The AND (or BIT) will generate the condition codes,
771  // but they are different from CMP.
772  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
773  // lowering & isel wouldn't diverge.
774  bool andCC = false;
775  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
776    if (RHSC->isNullValue() && LHS.hasOneUse() &&
777        (LHS.getOpcode() == ISD::AND ||
778         (LHS.getOpcode() == ISD::TRUNCATE &&
779          LHS.getOperand(0).getOpcode() == ISD::AND))) {
780      andCC = true;
781    }
782  }
783  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
784  SDValue TargetCC;
785  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
786
787  // Get the condition codes directly from the status register, if its easy.
788  // Otherwise a branch will be generated.  Note that the AND and BIT
789  // instructions generate different flags than CMP, the carry bit can be used
790  // for NE/EQ.
791  bool Invert = false;
792  bool Shift = false;
793  bool Convert = true;
794  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
795   default:
796    Convert = false;
797    break;
798   case MSP430CC::COND_HS:
799     // Res = SRW & 1, no processing is required
800     break;
801   case MSP430CC::COND_LO:
802     // Res = ~(SRW & 1)
803     Invert = true;
804     break;
805   case MSP430CC::COND_NE:
806     if (andCC) {
807       // C = ~Z, thus Res = SRW & 1, no processing is required
808     } else {
809       // Res = ~((SRW >> 1) & 1)
810       Shift = true;
811       Invert = true;
812     }
813     break;
814   case MSP430CC::COND_E:
815     Shift = true;
816     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
817     // Res = (SRW >> 1) & 1 is 1 word shorter.
818     break;
819  }
820  EVT VT = Op.getValueType();
821  SDValue One  = DAG.getConstant(1, VT);
822  if (Convert) {
823    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
824                                    MVT::i16, Flag);
825    if (Shift)
826      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
827      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
828    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
829    if (Invert)
830      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
831    return SR;
832  } else {
833    SDValue Zero = DAG.getConstant(0, VT);
834    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
835    SmallVector<SDValue, 4> Ops;
836    Ops.push_back(One);
837    Ops.push_back(Zero);
838    Ops.push_back(TargetCC);
839    Ops.push_back(Flag);
840    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
841  }
842}
843
844SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
845                                             SelectionDAG &DAG) const {
846  SDValue LHS    = Op.getOperand(0);
847  SDValue RHS    = Op.getOperand(1);
848  SDValue TrueV  = Op.getOperand(2);
849  SDValue FalseV = Op.getOperand(3);
850  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
851  DebugLoc dl    = Op.getDebugLoc();
852
853  SDValue TargetCC;
854  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
855
856  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
857  SmallVector<SDValue, 4> Ops;
858  Ops.push_back(TrueV);
859  Ops.push_back(FalseV);
860  Ops.push_back(TargetCC);
861  Ops.push_back(Flag);
862
863  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
864}
865
866SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
867                                               SelectionDAG &DAG) const {
868  SDValue Val = Op.getOperand(0);
869  EVT VT      = Op.getValueType();
870  DebugLoc dl = Op.getDebugLoc();
871
872  assert(VT == MVT::i16 && "Only support i16 for now!");
873
874  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
875                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
876                     DAG.getValueType(Val.getValueType()));
877}
878
879SDValue
880MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
881  MachineFunction &MF = DAG.getMachineFunction();
882  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
883  int ReturnAddrIndex = FuncInfo->getRAIndex();
884
885  if (ReturnAddrIndex == 0) {
886    // Set up a frame object for the return address.
887    uint64_t SlotSize = TD->getPointerSize();
888    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
889                                                           true);
890    FuncInfo->setRAIndex(ReturnAddrIndex);
891  }
892
893  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
894}
895
896SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
897                                              SelectionDAG &DAG) const {
898  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
899  MFI->setReturnAddressIsTaken(true);
900
901  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
902  DebugLoc dl = Op.getDebugLoc();
903
904  if (Depth > 0) {
905    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
906    SDValue Offset =
907      DAG.getConstant(TD->getPointerSize(), MVT::i16);
908    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
909                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
910                                   FrameAddr, Offset),
911                       MachinePointerInfo(), false, false, 0);
912  }
913
914  // Just load the return address.
915  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
916  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
917                     RetAddrFI, MachinePointerInfo(), false, false, 0);
918}
919
920SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
921                                             SelectionDAG &DAG) const {
922  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
923  MFI->setFrameAddressIsTaken(true);
924
925  EVT VT = Op.getValueType();
926  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
927  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
928  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
929                                         MSP430::FPW, VT);
930  while (Depth--)
931    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
932                            MachinePointerInfo(),
933                            false, false, 0);
934  return FrameAddr;
935}
936
937/// getPostIndexedAddressParts - returns true by value, base pointer and
938/// offset pointer and addressing mode by reference if this node can be
939/// combined with a load / store to form a post-indexed load / store.
940bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
941                                                      SDValue &Base,
942                                                      SDValue &Offset,
943                                                      ISD::MemIndexedMode &AM,
944                                                      SelectionDAG &DAG) const {
945
946  LoadSDNode *LD = cast<LoadSDNode>(N);
947  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
948    return false;
949
950  EVT VT = LD->getMemoryVT();
951  if (VT != MVT::i8 && VT != MVT::i16)
952    return false;
953
954  if (Op->getOpcode() != ISD::ADD)
955    return false;
956
957  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
958    uint64_t RHSC = RHS->getZExtValue();
959    if ((VT == MVT::i16 && RHSC != 2) ||
960        (VT == MVT::i8 && RHSC != 1))
961      return false;
962
963    Base = Op->getOperand(0);
964    Offset = DAG.getConstant(RHSC, VT);
965    AM = ISD::POST_INC;
966    return true;
967  }
968
969  return false;
970}
971
972
973const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
974  switch (Opcode) {
975  default: return NULL;
976  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
977  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
978  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
979  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
980  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
981  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
982  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
983  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
984  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
985  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
986  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
987  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
988  }
989}
990
991bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
992                                          Type *Ty2) const {
993  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
994    return false;
995
996  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
997}
998
999bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1000  if (!VT1.isInteger() || !VT2.isInteger())
1001    return false;
1002
1003  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1004}
1005
1006bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1007  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1008  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1009}
1010
1011bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1012  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1013  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1014}
1015
1016//===----------------------------------------------------------------------===//
1017//  Other Lowering Code
1018//===----------------------------------------------------------------------===//
1019
1020MachineBasicBlock*
1021MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1022                                     MachineBasicBlock *BB) const {
1023  MachineFunction *F = BB->getParent();
1024  MachineRegisterInfo &RI = F->getRegInfo();
1025  DebugLoc dl = MI->getDebugLoc();
1026  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1027
1028  unsigned Opc;
1029  const TargetRegisterClass * RC;
1030  switch (MI->getOpcode()) {
1031  default:
1032    assert(0 && "Invalid shift opcode!");
1033  case MSP430::Shl8:
1034   Opc = MSP430::SHL8r1;
1035   RC = MSP430::GR8RegisterClass;
1036   break;
1037  case MSP430::Shl16:
1038   Opc = MSP430::SHL16r1;
1039   RC = MSP430::GR16RegisterClass;
1040   break;
1041  case MSP430::Sra8:
1042   Opc = MSP430::SAR8r1;
1043   RC = MSP430::GR8RegisterClass;
1044   break;
1045  case MSP430::Sra16:
1046   Opc = MSP430::SAR16r1;
1047   RC = MSP430::GR16RegisterClass;
1048   break;
1049  case MSP430::Srl8:
1050   Opc = MSP430::SAR8r1c;
1051   RC = MSP430::GR8RegisterClass;
1052   break;
1053  case MSP430::Srl16:
1054   Opc = MSP430::SAR16r1c;
1055   RC = MSP430::GR16RegisterClass;
1056   break;
1057  }
1058
1059  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1060  MachineFunction::iterator I = BB;
1061  ++I;
1062
1063  // Create loop block
1064  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1065  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1066
1067  F->insert(I, LoopBB);
1068  F->insert(I, RemBB);
1069
1070  // Update machine-CFG edges by transferring all successors of the current
1071  // block to the block containing instructions after shift.
1072  RemBB->splice(RemBB->begin(), BB,
1073                llvm::next(MachineBasicBlock::iterator(MI)),
1074                BB->end());
1075  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1076
1077  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1078  BB->addSuccessor(LoopBB);
1079  BB->addSuccessor(RemBB);
1080  LoopBB->addSuccessor(RemBB);
1081  LoopBB->addSuccessor(LoopBB);
1082
1083  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1084  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1085  unsigned ShiftReg = RI.createVirtualRegister(RC);
1086  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1087  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1088  unsigned SrcReg = MI->getOperand(1).getReg();
1089  unsigned DstReg = MI->getOperand(0).getReg();
1090
1091  // BB:
1092  // cmp 0, N
1093  // je RemBB
1094  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1095    .addReg(ShiftAmtSrcReg).addImm(0);
1096  BuildMI(BB, dl, TII.get(MSP430::JCC))
1097    .addMBB(RemBB)
1098    .addImm(MSP430CC::COND_E);
1099
1100  // LoopBB:
1101  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1102  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1103  // ShiftReg2 = shift ShiftReg
1104  // ShiftAmt2 = ShiftAmt - 1;
1105  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1106    .addReg(SrcReg).addMBB(BB)
1107    .addReg(ShiftReg2).addMBB(LoopBB);
1108  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1109    .addReg(ShiftAmtSrcReg).addMBB(BB)
1110    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1111  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1112    .addReg(ShiftReg);
1113  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1114    .addReg(ShiftAmtReg).addImm(1);
1115  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1116    .addMBB(LoopBB)
1117    .addImm(MSP430CC::COND_NE);
1118
1119  // RemBB:
1120  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1121  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1122    .addReg(SrcReg).addMBB(BB)
1123    .addReg(ShiftReg2).addMBB(LoopBB);
1124
1125  MI->eraseFromParent();   // The pseudo instruction is gone now.
1126  return RemBB;
1127}
1128
1129MachineBasicBlock*
1130MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1131                                                  MachineBasicBlock *BB) const {
1132  unsigned Opc = MI->getOpcode();
1133
1134  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1135      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1136      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1137    return EmitShiftInstr(MI, BB);
1138
1139  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1140  DebugLoc dl = MI->getDebugLoc();
1141
1142  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1143         "Unexpected instr type to insert");
1144
1145  // To "insert" a SELECT instruction, we actually have to insert the diamond
1146  // control-flow pattern.  The incoming instruction knows the destination vreg
1147  // to set, the condition code register to branch on, the true/false values to
1148  // select between, and a branch opcode to use.
1149  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1150  MachineFunction::iterator I = BB;
1151  ++I;
1152
1153  //  thisMBB:
1154  //  ...
1155  //   TrueVal = ...
1156  //   cmpTY ccX, r1, r2
1157  //   jCC copy1MBB
1158  //   fallthrough --> copy0MBB
1159  MachineBasicBlock *thisMBB = BB;
1160  MachineFunction *F = BB->getParent();
1161  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1162  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1163  F->insert(I, copy0MBB);
1164  F->insert(I, copy1MBB);
1165  // Update machine-CFG edges by transferring all successors of the current
1166  // block to the new block which will contain the Phi node for the select.
1167  copy1MBB->splice(copy1MBB->begin(), BB,
1168                   llvm::next(MachineBasicBlock::iterator(MI)),
1169                   BB->end());
1170  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1171  // Next, add the true and fallthrough blocks as its successors.
1172  BB->addSuccessor(copy0MBB);
1173  BB->addSuccessor(copy1MBB);
1174
1175  BuildMI(BB, dl, TII.get(MSP430::JCC))
1176    .addMBB(copy1MBB)
1177    .addImm(MI->getOperand(3).getImm());
1178
1179  //  copy0MBB:
1180  //   %FalseValue = ...
1181  //   # fallthrough to copy1MBB
1182  BB = copy0MBB;
1183
1184  // Update machine-CFG edges
1185  BB->addSuccessor(copy1MBB);
1186
1187  //  copy1MBB:
1188  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1189  //  ...
1190  BB = copy1MBB;
1191  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1192          MI->getOperand(0).getReg())
1193    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1194    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1195
1196  MI->eraseFromParent();   // The pseudo instruction is gone now.
1197  return BB;
1198}
1199