1//=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrInfo.h" 16#include "PPCMachineFunctionInfo.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineModuleInfo.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/RegisterScavenging.h" 24#include "llvm/Target/TargetOptions.h" 25 26using namespace llvm; 27 28// FIXME This disables some code that aligns the stack to a boundary bigger than 29// the default (16 bytes on Darwin) when there is a stack local of greater 30// alignment. This does not currently work, because the delta between old and 31// new stack pointers is added to offsets that reference incoming parameters 32// after the prolog is generated, and the code that does that doesn't handle a 33// variable delta. You don't want to do that anyway; a better approach is to 34// reserve another register that retains to the incoming stack pointer, and 35// reference parameters relative to that. 36#define ALIGN_STACK 0 37 38 39/// VRRegNo - Map from a numbered VR register to its enum value. 40/// 41static const unsigned short VRRegNo[] = { 42 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 44 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 45 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 46}; 47 48/// RemoveVRSaveCode - We have found that this function does not need any code 49/// to manipulate the VRSAVE register, even though it uses vector registers. 50/// This can happen when the only registers used are known to be live in or out 51/// of the function. Remove all of the VRSAVE related code from the function. 52static void RemoveVRSaveCode(MachineInstr *MI) { 53 MachineBasicBlock *Entry = MI->getParent(); 54 MachineFunction *MF = Entry->getParent(); 55 56 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 57 MachineBasicBlock::iterator MBBI = MI; 58 ++MBBI; 59 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 60 MBBI->eraseFromParent(); 61 62 bool RemovedAllMTVRSAVEs = true; 63 // See if we can find and remove the MTVRSAVE instruction from all of the 64 // epilog blocks. 65 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 66 // If last instruction is a return instruction, add an epilogue 67 if (!I->empty() && I->back().getDesc().isReturn()) { 68 bool FoundIt = false; 69 for (MBBI = I->end(); MBBI != I->begin(); ) { 70 --MBBI; 71 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 72 MBBI->eraseFromParent(); // remove it. 73 FoundIt = true; 74 break; 75 } 76 } 77 RemovedAllMTVRSAVEs &= FoundIt; 78 } 79 } 80 81 // If we found and removed all MTVRSAVE instructions, remove the read of 82 // VRSAVE as well. 83 if (RemovedAllMTVRSAVEs) { 84 MBBI = MI; 85 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 86 --MBBI; 87 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 88 MBBI->eraseFromParent(); 89 } 90 91 // Finally, nuke the UPDATE_VRSAVE. 92 MI->eraseFromParent(); 93} 94 95// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 96// instruction selector. Based on the vector registers that have been used, 97// transform this into the appropriate ORI instruction. 98static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 99 MachineFunction *MF = MI->getParent()->getParent(); 100 DebugLoc dl = MI->getDebugLoc(); 101 102 unsigned UsedRegMask = 0; 103 for (unsigned i = 0; i != 32; ++i) 104 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 105 UsedRegMask |= 1 << (31-i); 106 107 // Live in and live out values already must be in the mask, so don't bother 108 // marking them. 109 for (MachineRegisterInfo::livein_iterator 110 I = MF->getRegInfo().livein_begin(), 111 E = MF->getRegInfo().livein_end(); I != E; ++I) { 112 unsigned RegNo = getPPCRegisterNumbering(I->first); 113 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 114 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 115 } 116 for (MachineRegisterInfo::liveout_iterator 117 I = MF->getRegInfo().liveout_begin(), 118 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 119 unsigned RegNo = getPPCRegisterNumbering(*I); 120 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122 } 123 124 // If no registers are used, turn this into a copy. 125 if (UsedRegMask == 0) { 126 // Remove all VRSAVE code. 127 RemoveVRSaveCode(MI); 128 return; 129 } 130 131 unsigned SrcReg = MI->getOperand(1).getReg(); 132 unsigned DstReg = MI->getOperand(0).getReg(); 133 134 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 135 if (DstReg != SrcReg) 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 137 .addReg(SrcReg) 138 .addImm(UsedRegMask); 139 else 140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 141 .addReg(SrcReg, RegState::Kill) 142 .addImm(UsedRegMask); 143 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 144 if (DstReg != SrcReg) 145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 146 .addReg(SrcReg) 147 .addImm(UsedRegMask >> 16); 148 else 149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 150 .addReg(SrcReg, RegState::Kill) 151 .addImm(UsedRegMask >> 16); 152 } else { 153 if (DstReg != SrcReg) 154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 155 .addReg(SrcReg) 156 .addImm(UsedRegMask >> 16); 157 else 158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 159 .addReg(SrcReg, RegState::Kill) 160 .addImm(UsedRegMask >> 16); 161 162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 163 .addReg(DstReg, RegState::Kill) 164 .addImm(UsedRegMask & 0xFFFF); 165 } 166 167 // Remove the old UPDATE_VRSAVE instruction. 168 MI->eraseFromParent(); 169} 170 171/// determineFrameLayout - Determine the size of the frame and maximum call 172/// frame size. 173void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { 174 MachineFrameInfo *MFI = MF.getFrameInfo(); 175 176 // Get the number of bytes to allocate from the FrameInfo 177 unsigned FrameSize = MFI->getStackSize(); 178 179 // Get the alignments provided by the target, and the maximum alignment 180 // (if any) of the fixed frame objects. 181 unsigned MaxAlign = MFI->getMaxAlignment(); 182 unsigned TargetAlign = getStackAlignment(); 183 unsigned AlignMask = TargetAlign - 1; // 184 185 // If we are a leaf function, and use up to 224 bytes of stack space, 186 // don't have a frame pointer, calls, or dynamic alloca then we do not need 187 // to adjust the stack pointer (we fit in the Red Zone). 188 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 189 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 190 if (!DisableRedZone && 191 FrameSize <= 224 && // Fits in red zone. 192 !MFI->hasVarSizedObjects() && // No dynamic alloca. 193 !MFI->adjustsStack() && // No calls. 194 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 195 // No need for frame 196 MFI->setStackSize(0); 197 return; 198 } 199 200 // Get the maximum call frame size of all the calls. 201 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 202 203 // Maximum call frame needs to be at least big enough for linkage and 8 args. 204 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 205 Subtarget.isDarwinABI()); 206 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 207 208 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 209 // that allocations will be aligned. 210 if (MFI->hasVarSizedObjects()) 211 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 212 213 // Update maximum call frame size. 214 MFI->setMaxCallFrameSize(maxCallFrameSize); 215 216 // Include call frame size in total. 217 FrameSize += maxCallFrameSize; 218 219 // Make sure the frame is aligned. 220 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 221 222 // Update frame info. 223 MFI->setStackSize(FrameSize); 224} 225 226// hasFP - Return true if the specified function actually has a dedicated frame 227// pointer register. 228bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 229 const MachineFrameInfo *MFI = MF.getFrameInfo(); 230 // FIXME: This is pretty much broken by design: hasFP() might be called really 231 // early, before the stack layout was calculated and thus hasFP() might return 232 // true or false here depending on the time of call. 233 return (MFI->getStackSize()) && needsFP(MF); 234} 235 236// needsFP - Return true if the specified function should have a dedicated frame 237// pointer register. This is true if the function has variable sized allocas or 238// if frame pointer elimination is disabled. 239bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 240 const MachineFrameInfo *MFI = MF.getFrameInfo(); 241 242 // Naked functions have no stack frame pushed, so we don't have a frame 243 // pointer. 244 if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 245 return false; 246 247 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() || 248 (GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 249} 250 251 252void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 253 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 254 MachineBasicBlock::iterator MBBI = MBB.begin(); 255 MachineFrameInfo *MFI = MF.getFrameInfo(); 256 const PPCInstrInfo &TII = 257 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 258 259 MachineModuleInfo &MMI = MF.getMMI(); 260 DebugLoc dl; 261 bool needsFrameMoves = MMI.hasDebugInfo() || 262 MF.getFunction()->needsUnwindTableEntry(); 263 264 // Prepare for frame info. 265 MCSymbol *FrameLabel = 0; 266 267 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 268 // process it. 269 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 270 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 271 HandleVRSaveUpdate(MBBI, TII); 272 break; 273 } 274 } 275 276 // Move MBBI back to the beginning of the function. 277 MBBI = MBB.begin(); 278 279 // Work out frame sizes. 280 // FIXME: determineFrameLayout() may change the frame size. This should be 281 // moved upper, to some hook. 282 determineFrameLayout(MF); 283 unsigned FrameSize = MFI->getStackSize(); 284 285 int NegFrameSize = -FrameSize; 286 287 // Get processor type. 288 bool isPPC64 = Subtarget.isPPC64(); 289 // Get operating system 290 bool isDarwinABI = Subtarget.isDarwinABI(); 291 // Check if the link register (LR) must be saved. 292 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 293 bool MustSaveLR = FI->mustSaveLR(); 294 // Do we have a frame pointer for this function? 295 bool HasFP = hasFP(MF); 296 297 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 298 299 int FPOffset = 0; 300 if (HasFP) { 301 if (Subtarget.isSVR4ABI()) { 302 MachineFrameInfo *FFI = MF.getFrameInfo(); 303 int FPIndex = FI->getFramePointerSaveIndex(); 304 assert(FPIndex && "No Frame Pointer Save Slot!"); 305 FPOffset = FFI->getObjectOffset(FPIndex); 306 } else { 307 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 308 } 309 } 310 311 if (isPPC64) { 312 if (MustSaveLR) 313 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 314 315 if (HasFP) 316 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 317 .addReg(PPC::X31) 318 .addImm(FPOffset/4) 319 .addReg(PPC::X1); 320 321 if (MustSaveLR) 322 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 323 .addReg(PPC::X0) 324 .addImm(LROffset / 4) 325 .addReg(PPC::X1); 326 } else { 327 if (MustSaveLR) 328 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 329 330 if (HasFP) 331 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 332 .addReg(PPC::R31) 333 .addImm(FPOffset) 334 .addReg(PPC::R1); 335 336 if (MustSaveLR) 337 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 338 .addReg(PPC::R0) 339 .addImm(LROffset) 340 .addReg(PPC::R1); 341 } 342 343 // Skip if a leaf routine. 344 if (!FrameSize) return; 345 346 // Get stack alignments. 347 unsigned TargetAlign = getStackAlignment(); 348 unsigned MaxAlign = MFI->getMaxAlignment(); 349 350 // Adjust stack pointer: r1 += NegFrameSize. 351 // If there is a preferred stack alignment, align R1 now 352 if (!isPPC64) { 353 // PPC32. 354 if (ALIGN_STACK && MaxAlign > TargetAlign) { 355 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 356 "Invalid alignment!"); 357 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 358 359 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 360 .addReg(PPC::R1) 361 .addImm(0) 362 .addImm(32 - Log2_32(MaxAlign)) 363 .addImm(31); 364 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 365 .addReg(PPC::R0, RegState::Kill) 366 .addImm(NegFrameSize); 367 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 368 .addReg(PPC::R1) 369 .addReg(PPC::R1) 370 .addReg(PPC::R0); 371 } else if (isInt<16>(NegFrameSize)) { 372 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 373 .addReg(PPC::R1) 374 .addImm(NegFrameSize) 375 .addReg(PPC::R1); 376 } else { 377 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 378 .addImm(NegFrameSize >> 16); 379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 380 .addReg(PPC::R0, RegState::Kill) 381 .addImm(NegFrameSize & 0xFFFF); 382 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 383 .addReg(PPC::R1) 384 .addReg(PPC::R1) 385 .addReg(PPC::R0); 386 } 387 } else { // PPC64. 388 if (ALIGN_STACK && MaxAlign > TargetAlign) { 389 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 390 "Invalid alignment!"); 391 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 392 393 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 394 .addReg(PPC::X1) 395 .addImm(0) 396 .addImm(64 - Log2_32(MaxAlign)); 397 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 398 .addReg(PPC::X0) 399 .addImm(NegFrameSize); 400 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 401 .addReg(PPC::X1) 402 .addReg(PPC::X1) 403 .addReg(PPC::X0); 404 } else if (isInt<16>(NegFrameSize)) { 405 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 406 .addReg(PPC::X1) 407 .addImm(NegFrameSize / 4) 408 .addReg(PPC::X1); 409 } else { 410 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 411 .addImm(NegFrameSize >> 16); 412 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 413 .addReg(PPC::X0, RegState::Kill) 414 .addImm(NegFrameSize & 0xFFFF); 415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 416 .addReg(PPC::X1) 417 .addReg(PPC::X1) 418 .addReg(PPC::X0); 419 } 420 } 421 422 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 423 424 // Add the "machine moves" for the instructions we generated above, but in 425 // reverse order. 426 if (needsFrameMoves) { 427 // Mark effective beginning of when frame pointer becomes valid. 428 FrameLabel = MMI.getContext().CreateTempSymbol(); 429 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 430 431 // Show update of SP. 432 if (NegFrameSize) { 433 MachineLocation SPDst(MachineLocation::VirtualFP); 434 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 435 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 436 } else { 437 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 438 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 439 } 440 441 if (HasFP) { 442 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 443 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 444 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 445 } 446 447 if (MustSaveLR) { 448 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 449 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 450 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 451 } 452 } 453 454 MCSymbol *ReadyLabel = 0; 455 456 // If there is a frame pointer, copy R1 into R31 457 if (HasFP) { 458 if (!isPPC64) { 459 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 460 .addReg(PPC::R1) 461 .addReg(PPC::R1); 462 } else { 463 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 464 .addReg(PPC::X1) 465 .addReg(PPC::X1); 466 } 467 468 if (needsFrameMoves) { 469 ReadyLabel = MMI.getContext().CreateTempSymbol(); 470 471 // Mark effective beginning of when frame pointer is ready. 472 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 473 474 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 475 (isPPC64 ? PPC::X1 : PPC::R1)); 476 MachineLocation FPSrc(MachineLocation::VirtualFP); 477 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 478 } 479 } 480 481 if (needsFrameMoves) { 482 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 483 484 // Add callee saved registers to move list. 485 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 486 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 487 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 488 unsigned Reg = CSI[I].getReg(); 489 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 490 491 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 492 // subregisters of CR2. We just need to emit a move of CR2. 493 if (PPC::CRBITRCRegisterClass->contains(Reg)) 494 continue; 495 496 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 497 MachineLocation CSSrc(Reg); 498 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 499 } 500 } 501} 502 503void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 504 MachineBasicBlock &MBB) const { 505 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 506 assert(MBBI != MBB.end() && "Returning block has no terminator"); 507 const PPCInstrInfo &TII = 508 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 509 510 unsigned RetOpcode = MBBI->getOpcode(); 511 DebugLoc dl; 512 513 assert((RetOpcode == PPC::BLR || 514 RetOpcode == PPC::TCRETURNri || 515 RetOpcode == PPC::TCRETURNdi || 516 RetOpcode == PPC::TCRETURNai || 517 RetOpcode == PPC::TCRETURNri8 || 518 RetOpcode == PPC::TCRETURNdi8 || 519 RetOpcode == PPC::TCRETURNai8) && 520 "Can only insert epilog into returning blocks"); 521 522 // Get alignment info so we know how to restore r1 523 const MachineFrameInfo *MFI = MF.getFrameInfo(); 524 unsigned TargetAlign = getStackAlignment(); 525 unsigned MaxAlign = MFI->getMaxAlignment(); 526 527 // Get the number of bytes allocated from the FrameInfo. 528 int FrameSize = MFI->getStackSize(); 529 530 // Get processor type. 531 bool isPPC64 = Subtarget.isPPC64(); 532 // Get operating system 533 bool isDarwinABI = Subtarget.isDarwinABI(); 534 // Check if the link register (LR) has been saved. 535 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 536 bool MustSaveLR = FI->mustSaveLR(); 537 // Do we have a frame pointer for this function? 538 bool HasFP = hasFP(MF); 539 540 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 541 542 int FPOffset = 0; 543 if (HasFP) { 544 if (Subtarget.isSVR4ABI()) { 545 MachineFrameInfo *FFI = MF.getFrameInfo(); 546 int FPIndex = FI->getFramePointerSaveIndex(); 547 assert(FPIndex && "No Frame Pointer Save Slot!"); 548 FPOffset = FFI->getObjectOffset(FPIndex); 549 } else { 550 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 551 } 552 } 553 554 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 555 RetOpcode == PPC::TCRETURNdi || 556 RetOpcode == PPC::TCRETURNai || 557 RetOpcode == PPC::TCRETURNri8 || 558 RetOpcode == PPC::TCRETURNdi8 || 559 RetOpcode == PPC::TCRETURNai8; 560 561 if (UsesTCRet) { 562 int MaxTCRetDelta = FI->getTailCallSPDelta(); 563 MachineOperand &StackAdjust = MBBI->getOperand(1); 564 assert(StackAdjust.isImm() && "Expecting immediate value."); 565 // Adjust stack pointer. 566 int StackAdj = StackAdjust.getImm(); 567 int Delta = StackAdj - MaxTCRetDelta; 568 assert((Delta >= 0) && "Delta must be positive"); 569 if (MaxTCRetDelta>0) 570 FrameSize += (StackAdj +Delta); 571 else 572 FrameSize += StackAdj; 573 } 574 575 if (FrameSize) { 576 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 577 // on entry to the function. Add this offset back now. 578 if (!isPPC64) { 579 // If this function contained a fastcc call and GuaranteedTailCallOpt is 580 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 581 // call which invalidates the stack pointer value in SP(0). So we use the 582 // value of R31 in this case. 583 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 584 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 585 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 586 .addReg(PPC::R31).addImm(FrameSize); 587 } else if(FI->hasFastCall()) { 588 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 589 .addImm(FrameSize >> 16); 590 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 591 .addReg(PPC::R0, RegState::Kill) 592 .addImm(FrameSize & 0xFFFF); 593 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 594 .addReg(PPC::R1) 595 .addReg(PPC::R31) 596 .addReg(PPC::R0); 597 } else if (isInt<16>(FrameSize) && 598 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 599 !MFI->hasVarSizedObjects()) { 600 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 601 .addReg(PPC::R1).addImm(FrameSize); 602 } else { 603 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 604 .addImm(0).addReg(PPC::R1); 605 } 606 } else { 607 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 608 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 609 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 610 .addReg(PPC::X31).addImm(FrameSize); 611 } else if(FI->hasFastCall()) { 612 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 613 .addImm(FrameSize >> 16); 614 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 615 .addReg(PPC::X0, RegState::Kill) 616 .addImm(FrameSize & 0xFFFF); 617 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 618 .addReg(PPC::X1) 619 .addReg(PPC::X31) 620 .addReg(PPC::X0); 621 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 622 !MFI->hasVarSizedObjects()) { 623 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 624 .addReg(PPC::X1).addImm(FrameSize); 625 } else { 626 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 627 .addImm(0).addReg(PPC::X1); 628 } 629 } 630 } 631 632 if (isPPC64) { 633 if (MustSaveLR) 634 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 635 .addImm(LROffset/4).addReg(PPC::X1); 636 637 if (HasFP) 638 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 639 .addImm(FPOffset/4).addReg(PPC::X1); 640 641 if (MustSaveLR) 642 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 643 } else { 644 if (MustSaveLR) 645 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 646 .addImm(LROffset).addReg(PPC::R1); 647 648 if (HasFP) 649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 650 .addImm(FPOffset).addReg(PPC::R1); 651 652 if (MustSaveLR) 653 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 654 } 655 656 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 657 // call optimization 658 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 659 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 660 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 661 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 662 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 663 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 664 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 665 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 666 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 667 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 668 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 669 670 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 671 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 672 .addReg(StackReg).addImm(CallerAllocatedAmt); 673 } else { 674 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 675 .addImm(CallerAllocatedAmt >> 16); 676 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 677 .addReg(TmpReg, RegState::Kill) 678 .addImm(CallerAllocatedAmt & 0xFFFF); 679 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 680 .addReg(StackReg) 681 .addReg(FPReg) 682 .addReg(TmpReg); 683 } 684 } else if (RetOpcode == PPC::TCRETURNdi) { 685 MBBI = MBB.getLastNonDebugInstr(); 686 MachineOperand &JumpTarget = MBBI->getOperand(0); 687 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 688 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 689 } else if (RetOpcode == PPC::TCRETURNri) { 690 MBBI = MBB.getLastNonDebugInstr(); 691 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 692 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 693 } else if (RetOpcode == PPC::TCRETURNai) { 694 MBBI = MBB.getLastNonDebugInstr(); 695 MachineOperand &JumpTarget = MBBI->getOperand(0); 696 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 697 } else if (RetOpcode == PPC::TCRETURNdi8) { 698 MBBI = MBB.getLastNonDebugInstr(); 699 MachineOperand &JumpTarget = MBBI->getOperand(0); 700 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 701 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 702 } else if (RetOpcode == PPC::TCRETURNri8) { 703 MBBI = MBB.getLastNonDebugInstr(); 704 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 705 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 706 } else if (RetOpcode == PPC::TCRETURNai8) { 707 MBBI = MBB.getLastNonDebugInstr(); 708 MachineOperand &JumpTarget = MBBI->getOperand(0); 709 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 710 } 711} 712 713static bool spillsCR(const MachineFunction &MF) { 714 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 715 return FuncInfo->isCRSpilled(); 716} 717 718/// MustSaveLR - Return true if this function requires that we save the LR 719/// register onto the stack in the prolog and restore it in the epilog of the 720/// function. 721static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 722 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 723 724 // We need a save/restore of LR if there is any def of LR (which is 725 // defined by calls, including the PIC setup sequence), or if there is 726 // some use of the LR stack slot (e.g. for builtin_return_address). 727 // (LR comes in 32 and 64 bit versions.) 728 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 729 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 730} 731 732void 733PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 734 RegScavenger *RS) const { 735 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 736 737 // Save and clear the LR state. 738 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 739 unsigned LR = RegInfo->getRARegister(); 740 FI->setMustSaveLR(MustSaveLR(MF, LR)); 741 MF.getRegInfo().setPhysRegUnused(LR); 742 743 // Save R31 if necessary 744 int FPSI = FI->getFramePointerSaveIndex(); 745 bool isPPC64 = Subtarget.isPPC64(); 746 bool isDarwinABI = Subtarget.isDarwinABI(); 747 MachineFrameInfo *MFI = MF.getFrameInfo(); 748 749 // If the frame pointer save index hasn't been defined yet. 750 if (!FPSI && needsFP(MF)) { 751 // Find out what the fix offset of the frame pointer save area. 752 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 753 // Allocate the frame index for frame pointer save area. 754 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 755 // Save the result. 756 FI->setFramePointerSaveIndex(FPSI); 757 } 758 759 // Reserve stack space to move the linkage area to in case of a tail call. 760 int TCSPDelta = 0; 761 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 762 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 763 } 764 765 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 766 // a large stack, which will require scavenging a register to materialize a 767 // large offset. 768 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 769 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 770 // r0 for now. 771 772 if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable. 773 if (needsFP(MF) || spillsCR(MF)) { 774 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 775 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 776 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 777 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 778 RC->getAlignment(), 779 false)); 780 } 781} 782 783void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) 784 const { 785 // Early exit if not using the SVR4 ABI. 786 if (!Subtarget.isSVR4ABI()) 787 return; 788 789 // Get callee saved register information. 790 MachineFrameInfo *FFI = MF.getFrameInfo(); 791 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 792 793 // Early exit if no callee saved registers are modified! 794 if (CSI.empty() && !needsFP(MF)) { 795 return; 796 } 797 798 unsigned MinGPR = PPC::R31; 799 unsigned MinG8R = PPC::X31; 800 unsigned MinFPR = PPC::F31; 801 unsigned MinVR = PPC::V31; 802 803 bool HasGPSaveArea = false; 804 bool HasG8SaveArea = false; 805 bool HasFPSaveArea = false; 806 bool HasCRSaveArea = false; 807 bool HasVRSAVESaveArea = false; 808 bool HasVRSaveArea = false; 809 810 SmallVector<CalleeSavedInfo, 18> GPRegs; 811 SmallVector<CalleeSavedInfo, 18> G8Regs; 812 SmallVector<CalleeSavedInfo, 18> FPRegs; 813 SmallVector<CalleeSavedInfo, 18> VRegs; 814 815 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 816 unsigned Reg = CSI[i].getReg(); 817 if (PPC::GPRCRegisterClass->contains(Reg)) { 818 HasGPSaveArea = true; 819 820 GPRegs.push_back(CSI[i]); 821 822 if (Reg < MinGPR) { 823 MinGPR = Reg; 824 } 825 } else if (PPC::G8RCRegisterClass->contains(Reg)) { 826 HasG8SaveArea = true; 827 828 G8Regs.push_back(CSI[i]); 829 830 if (Reg < MinG8R) { 831 MinG8R = Reg; 832 } 833 } else if (PPC::F8RCRegisterClass->contains(Reg)) { 834 HasFPSaveArea = true; 835 836 FPRegs.push_back(CSI[i]); 837 838 if (Reg < MinFPR) { 839 MinFPR = Reg; 840 } 841// FIXME SVR4: Disable CR save area for now. 842 } else if (PPC::CRBITRCRegisterClass->contains(Reg) 843 || PPC::CRRCRegisterClass->contains(Reg)) { 844// HasCRSaveArea = true; 845 } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 846 HasVRSAVESaveArea = true; 847 } else if (PPC::VRRCRegisterClass->contains(Reg)) { 848 HasVRSaveArea = true; 849 850 VRegs.push_back(CSI[i]); 851 852 if (Reg < MinVR) { 853 MinVR = Reg; 854 } 855 } else { 856 llvm_unreachable("Unknown RegisterClass!"); 857 } 858 } 859 860 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 861 862 int64_t LowerBound = 0; 863 864 // Take into account stack space reserved for tail calls. 865 int TCSPDelta = 0; 866 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 867 LowerBound = TCSPDelta; 868 } 869 870 // The Floating-point register save area is right below the back chain word 871 // of the previous stack frame. 872 if (HasFPSaveArea) { 873 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 874 int FI = FPRegs[i].getFrameIdx(); 875 876 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 877 } 878 879 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; 880 } 881 882 // Check whether the frame pointer register is allocated. If so, make sure it 883 // is spilled to the correct offset. 884 if (needsFP(MF)) { 885 HasGPSaveArea = true; 886 887 int FI = PFI->getFramePointerSaveIndex(); 888 assert(FI && "No Frame Pointer Save Slot!"); 889 890 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 891 } 892 893 // General register save area starts right below the Floating-point 894 // register save area. 895 if (HasGPSaveArea || HasG8SaveArea) { 896 // Move general register save area spill slots down, taking into account 897 // the size of the Floating-point register save area. 898 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 899 int FI = GPRegs[i].getFrameIdx(); 900 901 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 902 } 903 904 // Move general register save area spill slots down, taking into account 905 // the size of the Floating-point register save area. 906 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 907 int FI = G8Regs[i].getFrameIdx(); 908 909 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 910 } 911 912 unsigned MinReg = 913 std::min<unsigned>(getPPCRegisterNumbering(MinGPR), 914 getPPCRegisterNumbering(MinG8R)); 915 916 if (Subtarget.isPPC64()) { 917 LowerBound -= (31 - MinReg + 1) * 8; 918 } else { 919 LowerBound -= (31 - MinReg + 1) * 4; 920 } 921 } 922 923 // The CR save area is below the general register save area. 924 if (HasCRSaveArea) { 925 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 926 // which have the CR/CRBIT register class? 927 // Adjust the frame index of the CR spill slot. 928 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 929 unsigned Reg = CSI[i].getReg(); 930 931 if (PPC::CRBITRCRegisterClass->contains(Reg) || 932 PPC::CRRCRegisterClass->contains(Reg)) { 933 int FI = CSI[i].getFrameIdx(); 934 935 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 936 } 937 } 938 939 LowerBound -= 4; // The CR save area is always 4 bytes long. 940 } 941 942 if (HasVRSAVESaveArea) { 943 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 944 // which have the VRSAVE register class? 945 // Adjust the frame index of the VRSAVE spill slot. 946 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 947 unsigned Reg = CSI[i].getReg(); 948 949 if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 950 int FI = CSI[i].getFrameIdx(); 951 952 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 953 } 954 } 955 956 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 957 } 958 959 if (HasVRSaveArea) { 960 // Insert alignment padding, we need 16-byte alignment. 961 LowerBound = (LowerBound - 15) & ~(15); 962 963 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 964 int FI = VRegs[i].getFrameIdx(); 965 966 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 967 } 968 } 969} 970