1//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "reginfo"
16#include "PPC.h"
17#include "PPCInstrBuilder.h"
18#include "PPCMachineFunctionInfo.h"
19#include "PPCRegisterInfo.h"
20#include "PPCFrameLowering.h"
21#include "PPCSubtarget.h"
22#include "llvm/CallingConv.h"
23#include "llvm/Constants.h"
24#include "llvm/Function.h"
25#include "llvm/Type.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/RegisterScavenging.h"
33#include "llvm/Target/TargetFrameLowering.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/BitVector.h"
43#include "llvm/ADT/STLExtras.h"
44#include <cstdlib>
45
46#define GET_REGINFO_TARGET_DESC
47#include "PPCGenRegisterInfo.inc"
48
49// FIXME (64-bit): Eventually enable by default.
50namespace llvm {
51cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
52                                   cl::init(false),
53                                   cl::desc("Enable PPC32 register scavenger"),
54                                   cl::Hidden);
55cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
56                                   cl::init(false),
57                                   cl::desc("Enable PPC64 register scavenger"),
58                                   cl::Hidden);
59}
60
61using namespace llvm;
62
63// FIXME (64-bit): Should be inlined.
64bool
65PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
66  return ((EnablePPC32RS && !Subtarget.isPPC64()) ||
67          (EnablePPC64RS && Subtarget.isPPC64()));
68}
69
70PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
71                                 const TargetInstrInfo &tii)
72  : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
73                       ST.isPPC64() ? 0 : 1,
74                       ST.isPPC64() ? 0 : 1),
75    Subtarget(ST), TII(tii) {
76  ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
77  ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
78  ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
79  ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
80  ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
81  ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
82  ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
83  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
84
85  // 64-bit
86  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
87  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
88  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
89  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
90  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
91}
92
93/// getPointerRegClass - Return the register class to use to hold pointers.
94/// This is used for addressing modes.
95const TargetRegisterClass *
96PPCRegisterInfo::getPointerRegClass(unsigned Kind) const {
97  if (Subtarget.isPPC64())
98    return &PPC::G8RCRegClass;
99  return &PPC::GPRCRegClass;
100}
101
102const unsigned*
103PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
104  // 32-bit Darwin calling convention.
105  static const unsigned Darwin32_CalleeSavedRegs[] = {
106              PPC::R13, PPC::R14, PPC::R15,
107    PPC::R16, PPC::R17, PPC::R18, PPC::R19,
108    PPC::R20, PPC::R21, PPC::R22, PPC::R23,
109    PPC::R24, PPC::R25, PPC::R26, PPC::R27,
110    PPC::R28, PPC::R29, PPC::R30, PPC::R31,
111
112    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
113    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
114    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
115    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
116    PPC::F30, PPC::F31,
117
118    PPC::CR2, PPC::CR3, PPC::CR4,
119    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
120    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
121    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
122
123    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
124    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
125    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
126
127    PPC::LR,  0
128  };
129
130  // 32-bit SVR4 calling convention.
131  static const unsigned SVR4_CalleeSavedRegs[] = {
132                        PPC::R14, PPC::R15,
133    PPC::R16, PPC::R17, PPC::R18, PPC::R19,
134    PPC::R20, PPC::R21, PPC::R22, PPC::R23,
135    PPC::R24, PPC::R25, PPC::R26, PPC::R27,
136    PPC::R28, PPC::R29, PPC::R30, PPC::R31,
137
138    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
139    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
140    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
141    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
142    PPC::F30, PPC::F31,
143
144    PPC::CR2, PPC::CR3, PPC::CR4,
145
146    PPC::VRSAVE,
147
148    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
149    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
150    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
151
152    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
153    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
154    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
155
156    0
157  };
158  // 64-bit Darwin calling convention.
159  static const unsigned Darwin64_CalleeSavedRegs[] = {
160    PPC::X14, PPC::X15,
161    PPC::X16, PPC::X17, PPC::X18, PPC::X19,
162    PPC::X20, PPC::X21, PPC::X22, PPC::X23,
163    PPC::X24, PPC::X25, PPC::X26, PPC::X27,
164    PPC::X28, PPC::X29, PPC::X30, PPC::X31,
165
166    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
167    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
168    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
169    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
170    PPC::F30, PPC::F31,
171
172    PPC::CR2, PPC::CR3, PPC::CR4,
173    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
174    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
175    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
176
177    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
178    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
179    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
180
181    PPC::LR8,  0
182  };
183
184  // 64-bit SVR4 calling convention.
185  static const unsigned SVR4_64_CalleeSavedRegs[] = {
186    PPC::X14, PPC::X15,
187    PPC::X16, PPC::X17, PPC::X18, PPC::X19,
188    PPC::X20, PPC::X21, PPC::X22, PPC::X23,
189    PPC::X24, PPC::X25, PPC::X26, PPC::X27,
190    PPC::X28, PPC::X29, PPC::X30, PPC::X31,
191
192    PPC::F14, PPC::F15, PPC::F16, PPC::F17,
193    PPC::F18, PPC::F19, PPC::F20, PPC::F21,
194    PPC::F22, PPC::F23, PPC::F24, PPC::F25,
195    PPC::F26, PPC::F27, PPC::F28, PPC::F29,
196    PPC::F30, PPC::F31,
197
198    PPC::CR2, PPC::CR3, PPC::CR4,
199
200    PPC::VRSAVE,
201
202    PPC::V20, PPC::V21, PPC::V22, PPC::V23,
203    PPC::V24, PPC::V25, PPC::V26, PPC::V27,
204    PPC::V28, PPC::V29, PPC::V30, PPC::V31,
205
206    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
207    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
208    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
209
210    0
211  };
212
213  if (Subtarget.isDarwinABI())
214    return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs :
215                                 Darwin32_CalleeSavedRegs;
216
217  return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs;
218}
219
220BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
221  BitVector Reserved(getNumRegs());
222  const PPCFrameLowering *PPCFI =
223    static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
224
225  Reserved.set(PPC::R0);
226  Reserved.set(PPC::R1);
227  Reserved.set(PPC::LR);
228  Reserved.set(PPC::LR8);
229  Reserved.set(PPC::RM);
230
231  // The SVR4 ABI reserves r2 and r13
232  if (Subtarget.isSVR4ABI()) {
233    Reserved.set(PPC::R2);  // System-reserved register
234    Reserved.set(PPC::R13); // Small Data Area pointer register
235  }
236  // Reserve R2 on Darwin to hack around the problem of save/restore of CR
237  // when the stack frame is too big to address directly; we need two regs.
238  // This is a hack.
239  if (Subtarget.isDarwinABI()) {
240    Reserved.set(PPC::R2);
241  }
242
243  // On PPC64, r13 is the thread pointer. Never allocate this register.
244  // Note that this is over conservative, as it also prevents allocation of R31
245  // when the FP is not needed.
246  if (Subtarget.isPPC64()) {
247    Reserved.set(PPC::R13);
248    Reserved.set(PPC::R31);
249
250    if (!requiresRegisterScavenging(MF))
251      Reserved.set(PPC::R0);    // FIXME (64-bit): Remove
252
253    Reserved.set(PPC::X0);
254    Reserved.set(PPC::X1);
255    Reserved.set(PPC::X13);
256    Reserved.set(PPC::X31);
257
258    // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
259    if (Subtarget.isSVR4ABI()) {
260      Reserved.set(PPC::X2);
261    }
262    // Reserve R2 on Darwin to hack around the problem of save/restore of CR
263    // when the stack frame is too big to address directly; we need two regs.
264    // This is a hack.
265    if (Subtarget.isDarwinABI()) {
266      Reserved.set(PPC::X2);
267    }
268  }
269
270  if (PPCFI->needsFP(MF))
271    Reserved.set(PPC::R31);
272
273  return Reserved;
274}
275
276//===----------------------------------------------------------------------===//
277// Stack Frame Processing methods
278//===----------------------------------------------------------------------===//
279
280void PPCRegisterInfo::
281eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
282                              MachineBasicBlock::iterator I) const {
283  if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
284    // Add (actually subtract) back the amount the callee popped on return.
285    if (int CalleeAmt =  I->getOperand(1).getImm()) {
286      bool is64Bit = Subtarget.isPPC64();
287      CalleeAmt *= -1;
288      unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
289      unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
290      unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
291      unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
292      unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
293      unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
294      MachineInstr *MI = I;
295      DebugLoc dl = MI->getDebugLoc();
296
297      if (isInt<16>(CalleeAmt)) {
298        BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
299          addImm(CalleeAmt);
300      } else {
301        MachineBasicBlock::iterator MBBI = I;
302        BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
303          .addImm(CalleeAmt >> 16);
304        BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
305          .addReg(TmpReg, RegState::Kill)
306          .addImm(CalleeAmt & 0xFFFF);
307        BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
308          .addReg(StackReg)
309          .addReg(StackReg)
310          .addReg(TmpReg);
311      }
312    }
313  }
314  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
315  MBB.erase(I);
316}
317
318/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
319/// register first and then a spilled callee-saved register if that fails.
320static
321unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
322                             const TargetRegisterClass *RC, int SPAdj) {
323  assert(RS && "Register scavenging must be on");
324  unsigned Reg = RS->FindUnusedReg(RC);
325  // FIXME: move ARM callee-saved reg scan to target independent code, then
326  // search for already spilled CS register here.
327  if (Reg == 0)
328    Reg = RS->scavengeRegister(RC, II, SPAdj);
329  return Reg;
330}
331
332/// lowerDynamicAlloc - Generate the code for allocating an object in the
333/// current frame.  The sequence of code with be in the general form
334///
335///   addi   R0, SP, \#frameSize ; get the address of the previous frame
336///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
337///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
338///
339void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
340                                        int SPAdj, RegScavenger *RS) const {
341  // Get the instruction.
342  MachineInstr &MI = *II;
343  // Get the instruction's basic block.
344  MachineBasicBlock &MBB = *MI.getParent();
345  // Get the basic block's function.
346  MachineFunction &MF = *MBB.getParent();
347  // Get the frame info.
348  MachineFrameInfo *MFI = MF.getFrameInfo();
349  // Determine whether 64-bit pointers are used.
350  bool LP64 = Subtarget.isPPC64();
351  DebugLoc dl = MI.getDebugLoc();
352
353  // Get the maximum call stack size.
354  unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
355  // Get the total frame size.
356  unsigned FrameSize = MFI->getStackSize();
357
358  // Get stack alignments.
359  unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
360  unsigned MaxAlign = MFI->getMaxAlignment();
361  if (MaxAlign > TargetAlign)
362    report_fatal_error("Dynamic alloca with large aligns not supported");
363
364  // Determine the previous frame's address.  If FrameSize can't be
365  // represented as 16 bits or we need special alignment, then we load the
366  // previous frame's address from 0(SP).  Why not do an addis of the hi?
367  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
368  // Constructing the constant and adding would take 3 instructions.
369  // Fortunately, a frame greater than 32K is rare.
370  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
371  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
372  const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
373
374  // FIXME (64-bit): Use "findScratchRegister"
375  unsigned Reg;
376  if (requiresRegisterScavenging(MF))
377    Reg = findScratchRegister(II, RS, RC, SPAdj);
378  else
379    Reg = PPC::R0;
380
381  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
382    BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
383      .addReg(PPC::R31)
384      .addImm(FrameSize);
385  } else if (LP64) {
386    if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
387      BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
388        .addImm(0)
389        .addReg(PPC::X1);
390    else
391      BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
392        .addImm(0)
393        .addReg(PPC::X1);
394  } else {
395    BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
396      .addImm(0)
397      .addReg(PPC::R1);
398  }
399
400  // Grow the stack and update the stack pointer link, then determine the
401  // address of new allocated space.
402  if (LP64) {
403    if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
404      BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
405        .addReg(Reg, RegState::Kill)
406        .addReg(PPC::X1)
407        .addReg(MI.getOperand(1).getReg());
408    else
409      BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
410        .addReg(PPC::X0, RegState::Kill)
411        .addReg(PPC::X1)
412        .addReg(MI.getOperand(1).getReg());
413
414    if (!MI.getOperand(1).isKill())
415      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
416        .addReg(PPC::X1)
417        .addImm(maxCallFrameSize);
418    else
419      // Implicitly kill the register.
420      BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
421        .addReg(PPC::X1)
422        .addImm(maxCallFrameSize)
423        .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
424  } else {
425    BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
426      .addReg(Reg, RegState::Kill)
427      .addReg(PPC::R1)
428      .addReg(MI.getOperand(1).getReg());
429
430    if (!MI.getOperand(1).isKill())
431      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
432        .addReg(PPC::R1)
433        .addImm(maxCallFrameSize);
434    else
435      // Implicitly kill the register.
436      BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
437        .addReg(PPC::R1)
438        .addImm(maxCallFrameSize)
439        .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
440  }
441
442  // Discard the DYNALLOC instruction.
443  MBB.erase(II);
444}
445
446/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
447/// reserving a whole register (R0), we scrounge for one here. This generates
448/// code like this:
449///
450///   mfcr rA                  ; Move the conditional register into GPR rA.
451///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
452///   stw rA, FI               ; Store rA to the frame.
453///
454void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
455                                      unsigned FrameIndex, int SPAdj,
456                                      RegScavenger *RS) const {
457  // Get the instruction.
458  MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>, <FI>
459  // Get the instruction's basic block.
460  MachineBasicBlock &MBB = *MI.getParent();
461  DebugLoc dl = MI.getDebugLoc();
462
463  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
464  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
465  const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
466  unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
467  unsigned SrcReg = MI.getOperand(0).getReg();
468  bool LP64 = Subtarget.isPPC64();
469
470  // We need to store the CR in the low 4-bits of the saved value. First, issue
471  // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
472  BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg)
473          .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
474
475  // If the saved register wasn't CR0, shift the bits left so that they are in
476  // CR0's slot.
477  if (SrcReg != PPC::CR0)
478    // rlwinm rA, rA, ShiftBits, 0, 31.
479    BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
480      .addReg(Reg, RegState::Kill)
481      .addImm(getPPCRegisterNumbering(SrcReg) * 4)
482      .addImm(0)
483      .addImm(31);
484
485  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
486                    .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())),
487                    FrameIndex);
488
489  // Discard the pseudo instruction.
490  MBB.erase(II);
491}
492
493void
494PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
495                                     int SPAdj, RegScavenger *RS) const {
496  assert(SPAdj == 0 && "Unexpected");
497
498  // Get the instruction.
499  MachineInstr &MI = *II;
500  // Get the instruction's basic block.
501  MachineBasicBlock &MBB = *MI.getParent();
502  // Get the basic block's function.
503  MachineFunction &MF = *MBB.getParent();
504  // Get the frame info.
505  MachineFrameInfo *MFI = MF.getFrameInfo();
506  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
507  DebugLoc dl = MI.getDebugLoc();
508
509  // Find out which operand is the frame index.
510  unsigned FIOperandNo = 0;
511  while (!MI.getOperand(FIOperandNo).isFI()) {
512    ++FIOperandNo;
513    assert(FIOperandNo != MI.getNumOperands() &&
514           "Instr doesn't have FrameIndex operand!");
515  }
516  // Take into account whether it's an add or mem instruction
517  unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
518  if (MI.isInlineAsm())
519    OffsetOperandNo = FIOperandNo-1;
520
521  // Get the frame index.
522  int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
523
524  // Get the frame pointer save index.  Users of this index are primarily
525  // DYNALLOC instructions.
526  PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
527  int FPSI = FI->getFramePointerSaveIndex();
528  // Get the instruction opcode.
529  unsigned OpC = MI.getOpcode();
530
531  // Special case for dynamic alloca.
532  if (FPSI && FrameIndex == FPSI &&
533      (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
534    lowerDynamicAlloc(II, SPAdj, RS);
535    return;
536  }
537
538  // Special case for pseudo-op SPILL_CR.
539  if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default.
540    if (OpC == PPC::SPILL_CR) {
541      lowerCRSpilling(II, FrameIndex, SPAdj, RS);
542      return;
543    }
544
545  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
546  MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
547                                              PPC::R31 : PPC::R1,
548                                              false);
549
550  // Figure out if the offset in the instruction is shifted right two bits. This
551  // is true for instructions like "STD", which the machine implicitly adds two
552  // low zeros to.
553  bool isIXAddr = false;
554  switch (OpC) {
555  case PPC::LWA:
556  case PPC::LD:
557  case PPC::STD:
558  case PPC::STD_32:
559    isIXAddr = true;
560    break;
561  }
562
563  // Now add the frame object offset to the offset from r1.
564  int Offset = MFI->getObjectOffset(FrameIndex);
565  if (!isIXAddr)
566    Offset += MI.getOperand(OffsetOperandNo).getImm();
567  else
568    Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
569
570  // If we're not using a Frame Pointer that has been set to the value of the
571  // SP before having the stack size subtracted from it, then add the stack size
572  // to Offset to get the correct offset.
573  // Naked functions have stack size 0, although getStackSize may not reflect that
574  // because we didn't call all the pieces that compute it for naked functions.
575  if (!MF.getFunction()->hasFnAttr(Attribute::Naked))
576    Offset += MFI->getStackSize();
577
578  // If we can, encode the offset directly into the instruction.  If this is a
579  // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
580  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
581  // clear can be encoded.  This is extremely uncommon, because normally you
582  // only "std" to a stack slot that is at least 4-byte aligned, but it can
583  // happen in invalid code.
584  if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
585    if (isIXAddr)
586      Offset >>= 2;    // The actual encoded value has the low two bits zero.
587    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
588    return;
589  }
590
591  // The offset doesn't fit into a single register, scavenge one to build the
592  // offset in.
593  // FIXME: figure out what SPAdj is doing here.
594
595  // FIXME (64-bit): Use "findScratchRegister".
596  unsigned SReg;
597  if (requiresRegisterScavenging(MF))
598    SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
599  else
600    SReg = PPC::R0;
601
602  // Insert a set of rA with the full offset value before the ld, st, or add
603  BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
604    .addImm(Offset >> 16);
605  BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
606    .addReg(SReg, RegState::Kill)
607    .addImm(Offset);
608
609  // Convert into indexed form of the instruction:
610  //
611  //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
612  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
613  unsigned OperandBase;
614
615  if (OpC != TargetOpcode::INLINEASM) {
616    assert(ImmToIdxMap.count(OpC) &&
617           "No indexed form of load or store available!");
618    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
619    MI.setDesc(TII.get(NewOpcode));
620    OperandBase = 1;
621  } else {
622    OperandBase = OffsetOperandNo;
623  }
624
625  unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
626  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
627  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
628}
629
630unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
631  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
632
633  if (!Subtarget.isPPC64())
634    return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
635  else
636    return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
637}
638
639unsigned PPCRegisterInfo::getEHExceptionRegister() const {
640  return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
641}
642
643unsigned PPCRegisterInfo::getEHHandlerRegister() const {
644  return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
645}
646