dad13e3c08e7005854271e562eda4ffa5c71bc38 |
|
29-Sep-2014 |
Liviu Dudau <Liviu.Dudau@arm.com> |
ARM: Define PCI_IOBASE as the base of virtual PCI IO space This is needed for calls into OF code that parses PCI ranges. It signals support for memory mapped PCI I/O accesses that are described by device trees. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> CC: Russell King <linux@arm.linux.org.uk> CC: Rob Herring <robh+dt@kernel.org>
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1c8c3cf0b5239388e712508a85821f4718f4d889 |
|
19-May-2014 |
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type Due to a design incompatibility between the PCIe Marvell controller and the Cortex-A9, stressing PCIe devices with a lot of traffic quickly causes a deadlock. One part of the workaround for this is to have all PCIe regions mapped as strongly-ordered (MT_UNCACHED) instead of the default MT_DEVICE. While the arch_ioremap_caller() mechanism allows sub-architecture code to override ioremap(), used to map PCIe memory regions, there isn't such a mechanism to override the behavior of pci_ioremap_io(). This commit adds the arch_pci_ioremap_mem_type variable, initialized to MT_DEVICE by default, and that sub-architecture code can override. We have chosen to expose a single variable rather than offering the possibility of overriding the entire pci_ioremap_io(), because implementing pci_ioremap_io() requires calling functions (get_mem_type()) that are private to the arch/arm/mm/ code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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c5ca95b507c8a2a69e49eeda539b41bd76922d7f |
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18-Dec-2013 |
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> |
ARM: 7930/1: Introduce atomic MMIO modify Some SoC have MMIO regions that are shared across orthogonal subsystems. This commit implements a possible solution for the thread-safe access of such regions through a spinlock-protected API. Concurrent access is protected with a single spinlock for the entire MMIO address space. While this protects shared-registers, it also serializes access to unrelated/unshared registers. We add relaxed and non-relaxed variants, by using writel_relaxed and writel, respectively. The rationale for this is that some users may not require register write completion but only thread-safe access to a register. Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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0a5ccc86507f45b80831dac1049197c4d45be955 |
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03-Jan-2014 |
Rob Herring <rob.herring@calxeda.com> |
ARM: 7933/1: rename ioremap_cached to ioremap_cache ioremap_cache is more aligned with other architectures. There are only 2 users of this in the kernel: pxa2xx-flash and Xen. This fixes Xen build failures on arm64: drivers/tty/hvc/hvc_xen.c:233:2: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/grant-table.c:1174:3: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/xenbus/xenbus_probe.c:778:4: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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92341c83a904a23f9af52598cd97a8438b99eb00 |
|
22-Nov-2013 |
Rob Herring <rob.herring@calxeda.com> |
ARM: 7896/1: rename ioremap_cached to ioremap_cache ioremap_cache is more aligned with other architectures. There are only 2 users of this in the kernel: pxa2xx-flash and Xen. This fixes Xen build failures on arm64 caused by commit c04e8e2fe5 (arm64: allow ioremap_cache() to use existing RAM mappings) drivers/tty/hvc/hvc_xen.c:233:2: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/grant-table.c:1174:3: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/xenbus/xenbus_probe.c:778:4: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ffc555be09bd2603abdbc6f8b64c6a7477facc48 |
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06-Nov-2013 |
Stefano Stabellini <stefano.stabellini@eu.citrix.com> |
arm,arm64/include/asm/io.h: define struct bio_vec Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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3d1975b57097820c131c692d2e0d075641370369 |
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25-Oct-2013 |
Stefano Stabellini <stefano.stabellini@eu.citrix.com> |
arm,arm64: do not always merge biovec if we are running on Xen This is similar to what it is done on X86: biovecs are prevented from merging otherwise every dma requests would be forced to bounce on the swiotlb buffer. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Changes in v7: - remove the extra autotranslate check in biomerge.c.
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9b97173e785a54c5df0aa23d1e1f680f61e36e43 |
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16-May-2013 |
Laura Abbott <lauraa@codeaurora.org> |
ARM: 7728/1: mm: Use phys_addr_t properly for ioremap functions Several of the ioremap functions use unsigned long in places resulting in truncation if physical addresses greater than 4G are passed in. Change the types of the functions and the callers accordingly. Cc: Krzysztof Halasa <khc@pm.waw.pl> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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7629a9f661f72eb383fb896e59efea1eac74e882 |
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26-Oct-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7567/1: io: avoid GCC's offsettable addressing modes for halfword accesses Using the 'o' memory constraint in inline assembly can result in GCC generating invalid immediate offsets for memory access instructions with reduced addressing capabilities (i.e. smaller than 12-bit immediate offsets): http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54983 As there is no constraint to specify the exact addressing mode we need, fallback to using 'Q' exclusively for halfword I/O accesses. This may emit an additional add instruction (using an extra register) in order to construct the address but it will always be accepted by GAS. Reported-by: Bastian Hecht <hechtb@googlemail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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7e6735c3578e76c270a2797225a4214176ba13ef |
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12-Sep-2012 |
Cyril Chemparathy <cyril@ti.com> |
/dev/mem: use phys_addr_t for physical addresses This patch fixes the /dev/mem driver to use phys_addr_t for physical addresses. This is required on PAE systems, especially those that run entirely out of >4G physical memory space. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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195bbcac2e5c12f7fb99cdcc492c3000c5537f4a |
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24-Aug-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7500/1: io: avoid writeback addressing modes for __raw_ accessors Data aborts taken to hyp mode do not provide a valid instruction syndrome field in the HSR if the faulting instruction is a memory access using a writeback addressing mode. For hypervisors emulating MMIO accesses to virtual peripherals, taking such an exception requires disassembling the faulting instruction in order to determine the behaviour of the access. Since this requires manually walking the two stages of translation, the world must be stopped to prevent races against page aging in the guest, where the first-stage translation is invalidated after the hypervisor has translated to an IPA and the physical page is reused for something else. This patch avoids taking this heavy performance penalty when running Linux as a guest by ensuring that our I/O accessors do not make use of writeback addressing modes. Cc: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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c2794437091a4fda72c4a4f3567dd728dcc0c3c9 |
|
01-Mar-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: Add fixed PCI i/o mapping This adds a fixed virtual mapping for PCI i/o addresses. The mapping is located at the last 2MB of vmalloc region (0xfee00000-0xff000000). 2MB is used to align with PMD size, but IO_SPACE_LIMIT is 1MB. The space is reserved after .map_io and can be mapped at any time later with pci_ioremap_io. Platforms which need early i/o mapping (e.g. for vga console) can call pci_map_io_early in their .map_io function. This has changed completely from the 1st implementation which only supported creating the static mapping at .map_io. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Nicolas Pitre <nico@linaro.org>
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af06bb9f12990cae941816f9d7051dc5bf93c8a2 |
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25-May-2012 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: fix out[bwl]() out[bwl]() had a side effect that gcc read-back from the register after writing its value. This causes a problem for at least 3c589_cs, which spits out lots of "adapter failure, FIFO diagnostic register 2011." Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1ac02d795889d1828a66d4b3a3fd66492d1d7cf2 |
|
05-Apr-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: fix __io macro for PCMCIA With commit c334bc1 (ARM: make mach/io.h include optional), PCMCIA was broken. PCMCIA depends on __io() returning a valid i/o address, and most ARM platforms require IO_SPACE_LIMIT be set to 0xffffffff for PCMCIA. This needs a better fix with a fixed i/o address mapping, but for now we just restore things to the previous behavior. This fixes at91, omap1, pxa and sa11xx. pxa needs io.h if PCI is enabled, but PCMCIA is not. sa11xx already has IO_SPACE_LIMIT set to 0xffffffff, so it doesn't need an io.h. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Joachim Eastwood <joachim.eastwood@jotron.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Andrew Victor <linux@maxim.org.za> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Tested-by: Paul Parsons <lost.distance@yahoo.com> (pxa270) Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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9f97da78bf018206fb623cd351d454af2f105fe0 |
|
28-Mar-2012 |
David Howells <dhowells@redhat.com> |
Disintegrate asm/system.h for ARM Disintegrate asm/system.h for ARM. Signed-off-by: David Howells <dhowells@redhat.com> cc: Russell King <linux@arm.linux.org.uk> cc: linux-arm-kernel@lists.infradead.org
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6f6f6a70295c6a4f89c7aca015c5db247a79d609 |
|
10-Mar-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: create a common IOMEM definition Several platforms create IOMEM defines for casting to 'void __iomem *', and other platforms are incorrectly using __io() macro for the same purpose. This creates a common definition and removes all the platform specific versions. Rather than try to make linux/io.h and asm/io.h assembly safe, the assembly version of IOMEM is moved into asm/assembler.h. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Kevin Hilman <khilman@ti.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ryan Mallon <rmallon@gmail.com> Cc: Eric Miao <eric.y.miao@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Viresh Kumar <viresh.kumar@st.com> Cc: Rajeev Kumar <rajeev-dlh.kumar@st.com> Cc: Colin Cross <ccross@android.com> Cc: Olof Johansson <olof@lixom.net> Cc: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
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5621caac1d9514b568f986b55ce5494b1d119d40 |
|
11-Feb-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: kill off __mem_pci __mem_pci is only used to enable readl/writel and friends. Just condition this on readl being defined and remove all the __mem_pci defines. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Lennert Buytenhek <kernel@wantstofly.org> Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Krzysztof Halasa <khc@pm.waw.pl> Cc: Nicolas Pitre <nico@fluxnic.net> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Colin Cross <ccross@android.com> Cc: Olof Johansson <olof@lixom.net> Cc: Stephen Warren <swarren@nvidia.com>
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c334bc150524f833db3c76a0aaf55fb5044444e1 |
|
05-Mar-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: make mach/io.h include optional Add a kconfig option NEED_MACH_IO_H to conditionally include mach/io.h. Basing this on CONFIG_PCI and CONFIG_ISA doesn't quite work. Most ISA platforms don't need mach/io.h, but ebsa110 does. Most PCI platforms need mach/io.h for now, but ks8695 doesn't which means i/o accesses are broken. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Nicolas Pitre <nico@linaro.org>
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21a5365b03975e2425e030ad072f32a9dd3387fb |
|
06-Mar-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: remove compile time __arch_ioremap/__arch_iounmap Now that all custom ioremap/iounmap users are converted to runtime hook, remove the compile time defines. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Nicolas Pitre <nico@linaro.org>
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4fe7ef3a0811c33137ace0ed424dd0c01dd2d75e |
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11-Feb-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: provide runtime hook for ioremap/iounmap We have compile time over-ride of ioremap and iounmap, but an run-time override is needed for multi-platform builds. This adds an extra function pointer check, but ioremap is not peformance critical. The option for compile time selection remains. The caller variant is used here to provide correct caller information as ARM can only support level 0 for __builtin_return_address. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Nicolas Pitre <nico@linaro.org>
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e5bfb72ce2ce558b5a5a46cc5694001f0479c7f2 |
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24-Nov-2011 |
Michael S. Tsirkin <mst@redhat.com> |
arm: switch to GENERIC_PCI_IOMAP arm copied pci_iomap from generic code, probably to avoid pulling the rest of iomap.c in. Since that's in a separate file now, we can reuse the common implementation. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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6c5482d53f195d3ca61c9ec1be25b0f4a92575fe |
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12-Oct-2011 |
Tony Lindgren <tony@atomide.com> |
ARM: 7129/1: Add __arm_ioremap_exec for mapping external memory as MT_MEMORY This allows mapping external memory such as SRAM for use. This is needed for some small chunks of code, such as reprogramming SDRAM memory source clocks that can't be executed in SDRAM. Other use cases include some PM related code. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Andres Salomon <dilinger@queued.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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b0c1264f534a1cb3c52036a23a04d238434a0df6 |
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04-Oct-2011 |
Olof Johansson <olof@lixom.net> |
ARM: 7118/1: rename temp variable in read*_relaxed() This resolves the following sparse warning from readl() and other macros, which ends up embedding readl_relaxed() using the same variable. arch/arm/mach-tegra/dma.c:169:8: warning: symbol '__v' shadows an earlier one arch/arm/mach-tegra/dma.c:169:8: originally declared here Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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06901bd83412db5a31de7526e637101ed0c2c472 |
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03-Sep-2011 |
Arnd Bergmann <arnd@arndb.de> |
ARM: add io{read,write}{16,32}be functions These functions are used in some PCI drivers with big-endian MMIO space, and they are trivial to add here. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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395cf9691d72173d8cdaa613c5f0255f993af94b |
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15-Aug-2011 |
Paul Bolle <pebolle@tiscali.nl> |
doc: fix broken references There are numerous broken references to Documentation files (in other Documentation files, in comments, etc.). These broken references are caused by typo's in the references, and by renames or removals of the Documentation files. Some broken references are simply odd. Fix these broken references, sometimes by dropping the irrelevant text they were part of. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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04e1c83806e30ae339fc45def595960c7fef1697 |
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06-Jul-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: io: add a default IO_SPACE_LIMIT definition Add a default IO_SPACE_LIMIT definition. Explain the chosen value and suggest why platforms would want to make it larger. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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c1928022ef94662a88329e35fa0968b1be328b8e |
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30-Jan-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: io: ensure inb/outb() et.al. are properly ordered on ARMv6+ Ensure that the ISA/PCI IO space accessors are properly ordered on ARMv6+ architectures. These should always be ordered with respect to all other accesses. This also fixes __iormb() and __iowmb() not being visible to ioread/ iowrite if a platform defines its own MMIO accessors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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28257f7fdee0facc3b7f934e82c2485f27120d41 |
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08-Dec-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: io: simplify ioremap* and iounmap definitions We don't need to repeat the same definitions of the ioremap*(), once in terms of __arch_ioremap() and again in terms of __arm_ioremap(). Instead, if the platform hasn't provided an __arch_ioremap, define this to be __arm_ioremap, and only define the ioremap*() set using __arch_ioremap. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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a0b7bd0829194c03921915a68ee4a331ee394223 |
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08-Dec-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: io: make iounmap() a simple macro Defining iounmap() with arguments prevents it from being used as a function pointer, causing platforms to work around this. Instead, define it to be a simple macro. Do the same for __arch_io(re|un)map too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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087aaffcdf9c91667c93923fbc05fa8fb6bc7d3a |
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23-Sep-2010 |
Nicolas Pitre <nico@fluxnic.net> |
ARM: implement CONFIG_STRICT_DEVMEM by disabling access to RAM via /dev/mem There are very few legitimate use cases, if any, for directly accessing system RAM through /dev/mem. So let's mimic what they do on x86 and forbid it when CONFIG_STRICT_DEVMEM is turned on. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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b92b3612134faff171981fad4f0adb33f485e02e |
|
29-Jul-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Add barriers to io{read,write}{8,16,32} accessors as well The ioread/iowrite accessors also need barriers as they're used in place of readl/writel et.al. in portable drivers. Create __iormb() and __iowmb() which are conditionally defined to be barriers dependent on ARM_DMA_MEM_BUFFERABLE, and always use these macros in the accessors. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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79f64dbf68c8a9779a7e9a25e0a9f0217a25b57a |
|
28-Jul-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 6273/1: Add barriers to the I/O accessors if ARM_DMA_MEM_BUFFERABLE When the coherent DMA buffers are mapped as Normal Non-cacheable (ARM_DMA_MEM_BUFFERABLE enabled), buffer accesses are no longer ordered with Device memory accesses causing failures in device drivers that do not use the mandatory memory barriers before starting a DMA transfer. LKML discussions led to the conclusion that such barriers have to be added to the I/O accessors: http://thread.gmane.org/gmane.linux.kernel/683509/focus=686153 http://thread.gmane.org/gmane.linux.ide/46414 http://thread.gmane.org/gmane.linux.kernel.cross-arch/5250 This patch introduces a wmb() barrier to the write*() I/O accessors to handle the situations where Normal Non-cacheable writes are still in the processor (or L2 cache controller) write buffer before a DMA transfer command is issued. For the read*() accessors, a rmb() is introduced after the I/O to avoid speculative loads where the driver polls for a DMA transfer ready bit. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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e936771a76a7b61ca55a5142a3de835c2e196871 |
|
28-Jul-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: 6271/1: Introduce *_relaxed() I/O accessors This patch introduces readl*_relaxed()/write*_relaxed() as the main I/O accessors (when __mem_pci is defined). The standard read*()/write*() macros are now based on the relaxed accessors. This patch is in preparation for a subsequent patch which adds barriers to the I/O accessors. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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31aa8fd6fd30b0f36416df7d09619768d26b4332 |
|
18-Dec-2009 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Add caller information to ioremap This allows the procfs vmallocinfo file to show who created the ioremap regions. Note: __builtin_return_address(0) doesn't do what's expected if its used in an inline function, so we leave __arm_ioremap callers in such places alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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0560cf5aa51216b06874333a2fa26ca034d97bdb |
|
30-Nov-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Add a common typesafe __io implementation As Al did for Versatile in 2ad4f86b60b649fd7428265c08d73a3bd360c81b, add a typesafe __io implementation for platforms to use. Convert platforms to use this new simple typesafe implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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db5b7169474882fabbd811a4cf5c1bae3157e677 |
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07-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Remove MT_DEVICE_IXP2000 and associated definitions As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1ad77a876da48331451698cc4172c90ab9b6372f |
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05-Sep-2008 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 5241/1: provide ioremap_wc() This patch provides an ARM implementation of ioremap_wc(). We use different page table attributes depending on which CPU we are running on: - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four possible mapping types (CB=00/01/10/11). We can't use any of the cached memory types (CB=10/11), since that breaks coherency with peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and CB=01 (Uncached/Buffered) allows the hardware more freedom than CB=00, so we'll use that. (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores but isn't allowed to merge them, but there is no other mapping type we can use that allows the hardware to delay and merge stores, so we'll go with CB=01.) - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight difference that on these platforms, CB=01 actually _does_ allow merging stores. (If you want noncoalescing bufferable behavior on Xscale v1/v2, you need to use XCB=101.) - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100 mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal in ARMv6 parlance). The ARMv6 ARM explicitly says that any accesses to Normal memory can be merged, which makes Normal memory more suitable for _wc mappings than Device or Strongly Ordered memory, as the latter two mapping types are guaranteed to maintain transaction number, size and order. We use the Uncached variety of Normal mappings for the same reason that we can't use C=1 mappings on ARMv5. The xsc3 Architecture Specification documents TEXCB=00100 as being Uncacheable and allowing coalescing of writes, which is also just what we need. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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a09e64fbc0094e3073dbb09c3b4bfe4ab669244b |
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05-Aug-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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4baa9922430662431231ac637adedddbb0cfb2d7 |
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02-Aug-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] move include/asm-arm to arch/arm/include/asm Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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