| /arch/parisc/math-emu/ |
| H A D | dfcmp.c | 31 * dbl_fcmp(leftptr, rightptr, cond, status)
51 unsigned int cond, unsigned int *status)
73 && (Exception(cond) || Dbl_isone_signaling(leftp1)))
77 && (Exception(cond) || Dbl_isone_signaling(rightp1))) )
80 Set_status_cbit(Unordered(cond));
84 Set_status_cbit(Unordered(cond));
96 Set_status_cbit(Unordered(cond));
111 Set_status_cbit(Equal(cond));
115 Set_status_cbit(Lessthan(cond));
119 Set_status_cbit(Greaterthan(cond));
50 dbl_fcmp(dbl_floating_point * leftptr, dbl_floating_point * rightptr, unsigned int cond, unsigned int *status) argument
[all...] |
| H A D | sfcmp.c | 31 * sgl_fcmp(leftptr, rightptr, cond, status)
50 unsigned int cond, unsigned int *status)
73 && (Exception(cond) || Sgl_isone_signaling(left)))
77 && (Exception(cond) || Sgl_isone_signaling(right)) ) )
80 Set_status_cbit(Unordered(cond));
84 Set_status_cbit(Unordered(cond));
96 Set_status_cbit(Unordered(cond));
111 Set_status_cbit(Equal(cond));
115 Set_status_cbit(Lessthan(cond));
119 Set_status_cbit(Greaterthan(cond));
49 sgl_fcmp(sgl_floating_point * leftptr, sgl_floating_point * rightptr, unsigned int cond, unsigned int *status) argument
[all...] |
| /arch/xtensa/include/asm/ |
| H A D | asmmacro.h | 26 * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
32 * cond true condition (used in loop'cond')
64 .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond variable
75 loop\cond \at, 99f
|
| /arch/arm64/kvm/ |
| H A D | emulate.c | 71 int cond; local
78 cond = kvm_vcpu_get_condition(vcpu);
79 if (cond == 0xE)
84 if (cond < 0) {
94 /* The cond for this insn works out as the top 4 bits. */
95 cond = (it >> 4);
100 if (!((cc_map[cond] >> cpsr_cond) & 1))
118 unsigned long itbits, cond; local
127 cond = (cpsr & 0xe000) >> 13;
133 itbits = cond
[all...] |
| /arch/unicore32/include/asm/ |
| H A D | assembler.h | 64 .macro notcond, cond, nexti = .+8 variable
65 .ifc \cond, eq
67 .else; .ifc \cond, ne
69 .else; .ifc \cond, ea
71 .else; .ifc \cond, ub
73 .else; .ifc \cond, fs
75 .else; .ifc \cond, ns
77 .else; .ifc \cond, fv
79 .else; .ifc \cond, nv
81 .else; .ifc \cond, u
100 .macro usracc, instr, reg, ptr, inc, cond, rept, abort variable
119 .macro strusr, reg, ptr, inc, cond = al, rept = 1, abort = 9001f variable
120 usracc st, \\reg, \\ptr, \\inc, \\cond, \\rept, \\abort variable
123 .macro ldrusr, reg, ptr, inc, cond = al, rept = 1, abort = 9001f variable
124 usracc ld, \\reg, \\ptr, \\inc, \\cond, \\rept, \\abort variable
[all...] |
| /arch/sh/kernel/cpu/sh5/ |
| H A D | unwind.c | 239 int cond; local
268 cond = ((pc >= __MEMORY_START) && (fp >= __MEMORY_START) &&
|
| /arch/arm/include/asm/ |
| H A D | assembler.h | 119 .macro asm_trace_hardirqs_on_cond, cond
126 bl\cond trace_hardirqs_on
346 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() variable
349 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
351 \instr\cond\()\t\().w \reg, [\ptr, #\off]
362 .macro usracc, instr, reg, ptr, inc, cond, rept, abort variable
365 .ifnc \cond,al
367 itt \cond
369 ittt \cond
376 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abor variable
378 usraccoff \\instr, \\reg, \\ptr, \\inc, \\inc, \\cond, \\abort variable
406 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f variable
407 usracc str, \\reg, \\ptr, \\inc, \\cond, \\rept, \\abort variable
410 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f variable
411 usracc ldr, \\reg, \\ptr, \\inc, \\cond, \\rept, \\abort variable
[all...] |
| /arch/arm/kvm/ |
| H A D | emulate.c | 171 unsigned long cpsr, cond, insn; local
188 cond = (kvm_vcpu_get_hsr(vcpu) & HSR_COND) >> HSR_COND_SHIFT;
199 /* The cond for this insn works out as the top 4 bits. */
200 cond = (it >> 4);
204 insn = cond << 28;
220 unsigned long itbits, cond; local
229 cond = (cpsr & 0xe000) >> 13;
235 itbits = cond = 0;
240 cpsr |= cond << 13;
|
| /arch/mips/math-emu/ |
| H A D | cp1emu.c | 407 case mm_32f_74_op: /* c.cond.fmt */
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
702 unsigned int cond, cbit; local
949 cond = ctx->fcr31 & cbit;
956 cond = !cond;
968 if (cond) {
1081 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1082 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1100 * cond
1365 unsigned cond; local
[all...] |
| /arch/arm/net/ |
| H A D | bpf_jit_32.c | 115 static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx) argument
117 inst |= (cond << 28);
327 static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx) argument
329 _emit(cond, ARM_LDRB_I(ARM_R3, r_addr, 1), ctx);
330 _emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
331 _emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 3), ctx);
332 _emit(cond, ARM_LSL_I(ARM_R3, ARM_R3, 16), ctx);
333 _emit(cond, ARM_LDRB_I(ARM_R0, r_addr, 2), ctx);
334 _emit(cond, ARM_ORR_S(ARM_R3, ARM_R3, ARM_R1, SRTYPE_LSL, 24), ctx);
335 _emit(cond, ARM_ORR_
339 emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx) argument
363 emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx) argument
371 emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx) argument
418 emit_err_ret(u8 cond, struct jit_ctx *ctx) argument
[all...] |
| /arch/arm64/kernel/ |
| H A D | insn.c | 486 enum aarch64_insn_condition cond)
495 BUG_ON(cond < AARCH64_INSN_COND_EQ || cond > AARCH64_INSN_COND_AL);
496 insn |= cond;
485 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, enum aarch64_insn_condition cond) argument
|
| /arch/mips/net/ |
| H A D | bpf_jit.c | 511 static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2, argument
517 switch (cond) {
529 __func__, cond);
|