Searched defs:control (Results 226 - 250 of 317) sorted by relevance

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/drivers/tty/serial/
H A Dip22zilog.h9 volatile unsigned char control; member in struct:zilog_channel
13 volatile unsigned char control;
141 /* Write Register 9 (Master interrupt control) */
152 /* Write Register 10 (misc control bits) */
164 /* Write Register 11 (Clock Mode control) */
184 /* Write Register 14 (Misc control bits) */
198 /* Write Register 15 (external/status interrupt control) */
268 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
271 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
H A Dsunzilog.h5 volatile unsigned char control; member in struct:zilog_channel
142 /* Write Register 9 (Master interrupt control) */
154 /* Write Register 10 (misc control bits) */
166 /* Write Register 11 (Clock Mode control) */
186 /* Write Register 14 (Misc control bits) */
200 /* Write Register 15 (external/status interrupt control) */
276 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
279 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
/drivers/usb/gadget/udc/
H A Dgr_udc.c72 static const char * const gr_modestring[] = {"control", "iso", "bulk", "int"};
190 u32 control = gr_read32(&dev->regs->control); local
197 (control & GR_CONTROL_UA_MASK) >> GR_CONTROL_UA_POS);
785 gr_write32(&dev->regs->control, 0);
816 u32 control; local
823 control = gr_read32(&dev->regs->control);
824 control |= GR_CONTROL_TM | (dev->test_mode << GR_CONTROL_TS_POS);
825 gr_write32(&dev->regs->control, contro
893 u32 control; local
1191 u32 control; local
1899 u32 control; local
[all...]
/drivers/usb/musb/
H A Dmusb_core.h324 struct list_head control; /* of musb_qh */ member in struct:musb
/drivers/usb/phy/
H A Dphy-fsl-usb.h51 /* bit 23-16 are interrupt threshold control */
120 /* bit 15-14 are port indicator control */
127 /* bit 19-16 are port test control */
199 /* control Register Bit Masks */
346 u32 control; /* General Purpose Control Register */ member in struct:usb_dr_mmap
/drivers/video/fbdev/
H A Dcirrusfb.c670 unsigned int control = 0, format = 0, threshold = 0; local
878 control = fb_readw(cinfo->laguna_mmio + 0x402);
880 control &= ~0x6800;
908 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
917 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1119 control |= 0x2000;
1177 control |= 0x4000;
1245 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1555 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1622 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control
[all...]
H A Dsm501fb.c637 unsigned long control; /* control register */ local
647 control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
649 control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
659 control |= SM501_DC_CRT_CONTROL_HSP;
662 control |= SM501_DC_CRT_CONTROL_VSP;
664 if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
681 control |= SM501_FIFO_3; /* fill if >3 free slots */
685 control |= SM501_DC_CRT_CONTROL_8BPP;
689 control |
717 unsigned long control; local
807 unsigned long control; local
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/drivers/dma/
H A Dcoh901318.c175 * @ctrl_lli_last: DMA control register for the last lli in the list
176 * @ctrl_lli: DMA control register for an lli
177 * @ctrl_lli_chained: DMA control register for a chained lli
1323 i, l, l->control, l->src_addr, l->dst_addr,
1439 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) argument
1444 writel(control,
1502 writel(lli->control, virtbase + COH901318_CX_CTRL +
1599 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
2273 * Add runtime-specific control on top, make
2347 cohd->head_ctrl = lli->control;
[all...]
/drivers/media/platform/ti-vpe/
H A Dvpdma_priv.h512 * control descriptor
533 /* control descriptor types */
590 static inline u32 ctd_type_source_ctl(int source, int control) argument
593 (source << CTD_SOURCE_SHFT) | control;
/drivers/net/ethernet/altera/
H A Daltera_tse.h126 u32 control; /* PHY device operation control register */ member in struct:altera_tse_mdio
178 /* The host processor uses this register to control and configure the
315 /* FIFO control register */
470 /* Rx DMA & interrupt control protection */
/drivers/net/ethernet/atheros/atlx/
H A Datl1.c329 u32 control; local
336 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
337 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
342 control = ioread32(hw->hw_addr + REG_VPD_CAP);
343 if (control & VPD_CAP_VPD_FLAG)
346 if (control & VPD_CAP_VPD_FLAG) {
438 u32 i, control; local
455 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
458 addr[0] = control;
460 addr[1] = control;
[all...]
/drivers/net/ethernet/
H A Dfealnx.c165 FAR0 = 0x10, /* flow-control address 0-3 */
166 FAR1 = 0x14, /* flow-control address 4-5 */
176 FTH = 0x3C, /* flow control high/low threshold */
180 BMCRSR = 0x4c, /* basic mode control and status */
191 RFCON = 0x00020000, /* receive flow control xon packet */
192 RFCOFF = 0x00010000, /* receive flow control xoff packet */
240 s32 control; member in struct:fealnx_desc
268 RXIC = 0x00800000, /* interrupt control */
286 TXIC = 0x80000000, /* interrupt control */
290 CRCEnable = 0x08000000, /* crc control */
[all...]
/drivers/net/ethernet/marvell/
H A Dskge.c141 * Returns copy of whole control register region
216 /* Set GMAC to no flow control and auto update for speed/duplex */
225 /* Turn on appropriate WOL control bits */
956 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
975 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
989 rd->control = 0;
1057 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1982 /* Set Flow-control capabilities */
2123 /* disable Rx flow-control */
2128 /* enable Tx & Rx flow-control */
2738 u32 control, len; local
2854 skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e, u32 control) argument
3049 skge_rx_get(struct net_device *dev, struct skge_element *e, u32 control, u32 status, u16 csum) argument
3160 u32 control = ((const struct skge_tx_desc *) e->desc)->control; local
3212 u32 control; local
[all...]
/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_main.c407 u32 control = 0; local
422 pci_read_config_dword(pdev, pos + 0x10, &control);
423 if ((control & 0x000F0000) != 0x00020000) {
449 pci_read_config_dword(pdev, pos + 8, &control);
450 pci_read_config_dword(pdev, pos + 8, &control);
459 u32 control; local
462 pci_read_config_dword(pdev, pdev->msix_cap, &control);
464 control |= PCI_MSIX_FLAGS_ENABLE;
466 control = 0;
467 pci_write_config_dword(pdev, pdev->msix_cap, control);
[all...]
/drivers/net/wireless/ath/ath10k/
H A Dmac.c2303 struct ieee80211_tx_control *control,
2308 struct ieee80211_vif *vif = info->control.vif;
2309 struct ieee80211_key_conf *key = info->control.hw_key;
4037 if (mask->control[band].legacy != legacy)
4041 if (mask->control[band].ht_mcs[i] != ht)
4045 if (mask->control[band].vht_mcs[i] != vht)
4059 if (ath10k_check_single_mask(mask->control[band].legacy))
4064 if (mask->control[band].ht_mcs[i] == 0xff)
4066 else if (mask->control[band].ht_mcs[i] == 0x00)
4076 if (mask->control[ban
2302 ath10k_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument
[all...]
/drivers/net/wireless/b43legacy/
H A Dmain.c275 u32 control; local
279 control = routing;
280 control <<= 16;
281 control |= offset;
282 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
954 /* Convert a b43legacy antenna number value to the PHY TX control value. */
988 /* Write the PHY TX control parameters. */
1120 /* Set the frame control. */
2145 /* FIXME We also need to set the other flags of the PHY control
2187 /* Initialize the MAC control */
2519 b43legacy_op_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument
[all...]
/drivers/net/wireless/brcm80211/brcmsmac/
H A Ddma.c51 /* transmit channel control */
83 /* receive channel control */
149 /* descriptor control flags 1 */
156 /* descriptor control flags 2 */
165 /* control flags in the range [27:20] are core-specific and not defined here */
201 __le32 ctrl1; /* misc control bits & bufcount */
361 u32 control; local
363 control = bcma_read32(di->core, DMA64TXREGOFFS(di, control));
364 bcma_write32(di->core, DMA64TXREGOFFS(di, control),
825 u32 control; local
1141 u32 control = D64_XC_XE; local
[all...]
/drivers/net/wireless/iwlegacy/
H A D3945-mac.c389 TX_CMD_SEC_WEP | (info->control.hw_key->
396 info->control.hw_key->hw_key_idx);
567 if (info->control.hw_key)
2879 struct ieee80211_tx_control *control,
2889 if (il3945_tx_skb(il, control->sta, skb))
3918 pr_err("Unable to register rate control algorithm: %d\n", ret);
2878 il3945_mac_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument
/drivers/net/wireless/
H A Dmac80211_hwsim.c58 MODULE_PARM_DESC(rctbl, "Handle rate control table");
899 /* We get the tx control (rate and retries) info*/
970 if (info->control.rates[0].flags & IEEE80211_TX_RC_VHT_MCS) {
972 ieee80211_rate_get_vht_mcs(&info->control.rates[0]);
974 ieee80211_rate_get_vht_nss(&info->control.rates[0]);
977 rx_status.rate_idx = info->control.rates[0].idx;
978 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS)
981 if (info->control.rates[0].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
983 if (info->control.rates[0].flags & IEEE80211_TX_RC_SHORT_GI)
1077 struct ieee80211_tx_control *control,
1076 mac80211_hwsim_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) argument
[all...]
/drivers/scsi/lpfc/
H A Dlpfc_hbadisc.c631 uint32_t ha_copy, status, control, work_port_events; local
737 control = readl(phba->HCregaddr);
738 if (!(control & (HC_R0INT_ENA << LPFC_ELS_RING))) {
741 control, ha_copy, 0);
743 control |= (HC_R0INT_ENA << LPFC_ELS_RING);
744 writel(control, phba->HCregaddr);
749 control, ha_copy, 0);
1055 uint32_t control; local
1078 control = readl(phba->HCregaddr);
1079 control |
3255 uint32_t control; local
[all...]
/drivers/scsi/megaraid/
H A Dmegaraid_sas_base.c5014 u16 control = 0; local
5022 &control);
5023 if (control & PCI_MSIX_FLAGS_ENABLE) {
5027 control &
/drivers/scsi/qla2xxx/
H A Dqla_nx.c1632 u32 control; local
1639 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1640 val = control + QLA82XX_MSIX_TBL_SPACE;
1769 /* Setup ring parameters in initialization control block. */
/drivers/staging/rtl8712/
H A Dwifi.h80 /* below is for control frame */
524 unsigned short control; member in struct:ieee80211_bar
528 /* 802.11 BAR control masks */
/drivers/tty/
H A Dmxser.c240 int MCR; /* Modem control register */
710 /* CTS flow control flag and modem status interrupts */
1328 unsigned char control, status; local
1337 control = info->MCR;
1344 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1345 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
2009 * control, which is currently the case. Hence, if it ever
2788 } /* else: we have some ISA cards under control */
H A Dn_gsm.c26 * all control traffic via it
152 /* Flow control */
169 * DLCI 0 is used to pass control blocks out of band of the data
225 u8 control; member in struct:gsm_mux
434 /* FC is true flow control not modem bits */
453 * @control: control including PF bit
462 u8 control, const u8 *data, int dlen)
469 switch (control & ~PF) {
489 if (!(control
461 gsm_print_packet(const char *hdr, int addr, int cr, u8 control, const u8 *data, int dlen) argument
572 gsm_send(struct gsm_mux *gsm, int addr, int cr, int control) argument
619 gsm_response(struct gsm_mux *gsm, int addr, int control) argument
633 gsm_command(struct gsm_mux *gsm, int addr, int control) argument
1400 gsm_control_wait(struct gsm_mux *gsm, struct gsm_control *control) argument
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