/drivers/clocksource/ |
H A D | time-orion.c | 37 static void __iomem *timer_base; variable 44 return ~readl(timer_base + TIMER0_VAL); 56 writel(delta, timer_base + TIMER1_VAL); 57 atomic_io_modify(timer_base + TIMER_CTRL, 68 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD); 69 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL); 70 atomic_io_modify(timer_base + TIMER_CTRL, 75 atomic_io_modify(timer_base + TIMER_CTRL, 107 timer_base = of_iomap(np, 0); 108 if (!timer_base) [all...] |
H A D | bcm_kona_timer.c | 71 kona_timer_get_counter(void *timer_base, uint32_t *msw, uint32_t *lsw) argument 73 void __iomem *base = IOMEM(timer_base);
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H A D | meson6_timer.c | 39 static void __iomem *timer_base; variable 43 return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID)); 48 u32 val = readl(timer_base + TIMER_ISA_MUX); 50 writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); 55 writel(delay, timer_base + TIMER_ISA_VAL(timer)); 60 u32 val = readl(timer_base + TIMER_ISA_MUX); 67 writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); 130 timer_base = of_io_request_and_map(node, 0, "meson6-timer"); 131 if (IS_ERR(timer_base)) 139 val = readl(timer_base [all...] |
H A D | sun4i_timer.c | 42 static void __iomem *timer_base; variable 53 u32 old = readl(timer_base + TIMER_CNTVAL_REG(1)); 55 while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) 61 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); 62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer)); 68 writel(delay, timer_base + TIMER_INTVAL_REG(timer)); 73 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); 81 timer_base + TIMER_CTL_REG(timer)); 128 writel(0x1, timer_base + TIMER_IRQ_ST_REG); 143 return ~readl(timer_base [all...] |
H A D | vf_pit_timer.c | 165 void __iomem *timer_base; local 169 timer_base = of_iomap(np, 0); 170 BUG_ON(!timer_base); 177 clksrc_base = timer_base + PITn_OFFSET(2); 178 clkevt_base = timer_base + PITn_OFFSET(3); 192 __raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
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H A D | pxa_timer.c | 52 #define timer_readl(reg) readl_relaxed(timer_base + (reg)) 53 #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg)) 55 static void __iomem *timer_base; variable 177 clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200, 189 timer_base = of_iomap(np, 0); 190 if (!timer_base) 219 timer_base = base;
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H A D | time-armada-370-xp.c | 76 static void __iomem *timer_base, *local_base; variable 96 return ~readl(timer_base + TIMER0_VAL_OFF); 231 timer_base = of_iomap(np, 0); 232 WARN_ON(!timer_base); 242 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); 257 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); 258 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); 260 atomic_io_modify(timer_base + TIMER_CTRL_OFF, 269 clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
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H A D | timer-sun5i.c | 40 static void __iomem *timer_base; variable 51 u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1)); 53 while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) 59 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); 60 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer)); 67 writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer)); 72 u32 val = readl(timer_base + TIMER_CTL_REG(timer)); 80 timer_base + TIMER_CTL_REG(timer)); 127 writel(0x1, timer_base + TIMER_IRQ_ST_REG); 142 return ~readl(timer_base [all...] |
/drivers/staging/comedi/drivers/ |
H A D | das16m1.c | 256 unsigned long timer_base = dev->iobase + DAS16M1_8254_SECOND; local 258 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 259 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 261 i8254_write(timer_base, 0, 1, devpriv->divisor1); 262 i8254_write(timer_base, 0, 2, devpriv->divisor2); 271 unsigned long timer_base = dev->iobase + DAS16M1_8254_FIRST; local 283 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 284 i8254_write(timer_base, 0, 1, 0); 287 devpriv->initial_hw_count = i8254_read(timer_base, 0, 1);
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H A D | ni_at_ao.c | 294 unsigned long timer_base = dev->iobase + ATAO_82C53_BASE; local 302 i8254_set_mode(timer_base, 0, 0, I8254_MODE4 | I8254_BINARY); 303 i8254_set_mode(timer_base, 0, 1, I8254_MODE4 | I8254_BINARY); 304 i8254_write(timer_base, 0, 0, 0x0003);
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H A D | das800.c | 279 unsigned long timer_base = dev->iobase + DAS800_8254; local 281 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 282 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 283 i8254_write(timer_base, 0, 1, devpriv->divisor1); 284 i8254_write(timer_base, 0, 2, devpriv->divisor2);
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H A D | pcl711.c | 365 unsigned long timer_base = dev->iobase + PCL711_TIMER_BASE; local 367 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 368 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 370 i8254_write(timer_base, 0, 1, devpriv->divisor1); 371 i8254_write(timer_base, 0, 2, devpriv->divisor2);
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H A D | adl_pci9111.c | 175 unsigned long timer_base = dev->iobase + PCI9111_8254_BASE_REG; local 177 i8254_set_mode(timer_base, 1, 0, I8254_MODE0 | I8254_BINARY); 178 i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY); 179 i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY); 183 i8254_write(timer_base, 1, 2, dev_private->div2); 184 i8254_write(timer_base, 1, 1, dev_private->div1);
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H A D | das16.c | 737 unsigned long timer_base = dev->iobase + DAS16_TIMER_BASE_REG; local 743 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 744 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 745 i8254_write(timer_base, 0, 1, devpriv->divisor1); 746 i8254_write(timer_base, 0, 2, devpriv->divisor2);
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H A D | dt3000.c | 370 static int dt3k_ns_to_timer(unsigned int timer_base, unsigned int *nanosec, argument 379 base = timer_base * (prescale + 1); 399 base = timer_base * (1 << prescale);
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H A D | ni_at_a2150.c | 509 unsigned long timer_base = dev->iobase + I8253_BASE_REG; local 577 i8254_set_mode(timer_base, 0, 2, I8254_MODE0 | I8254_BINARY); 578 i8254_write(timer_base, 0, 2, 72);
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H A D | pcl812.c | 537 unsigned long timer_base = dev->iobase + PCL812_TIMER_BASE; local 539 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 540 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 544 i8254_write(timer_base, 0, 2, devpriv->divisor2); 545 i8254_write(timer_base, 0, 1, devpriv->divisor1);
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H A D | pcl816.c | 136 unsigned long timer_base = dev->iobase + PCL816_TIMER_BASE; local 138 i8254_set_mode(timer_base, 0, 0, I8254_MODE1 | I8254_BINARY); 139 i8254_write(timer_base, 0, 0, 0x00ff); 142 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 143 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 147 i8254_write(timer_base, 0, 2, devpriv->divisor2); 148 i8254_write(timer_base, 0, 1, devpriv->divisor1); 656 unsigned long timer_base = dev->iobase + PCL816_TIMER_BASE; local 663 i8254_set_mode(timer_base, 0, 2, I8254_MODE0 | I8254_BINARY); 664 i8254_set_mode(timer_base, [all...] |
H A D | pcl818.c | 332 unsigned long timer_base = dev->iobase + PCL818_TIMER_BASE; local 334 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 335 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 339 i8254_write(timer_base, 0, 2, devpriv->divisor2); 340 i8254_write(timer_base, 0, 1, devpriv->divisor1); 984 unsigned long timer_base = dev->iobase + PCL818_TIMER_BASE; local 1002 i8254_set_mode(timer_base, 0, 2, I8254_MODE0 | I8254_BINARY); 1003 i8254_set_mode(timer_base, 0, 1, I8254_MODE0 | I8254_BINARY); 1004 i8254_set_mode(timer_base, 0, 0, I8254_MODE0 | I8254_BINARY);
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H A D | adv_pci1710.c | 577 unsigned long timer_base = dev->iobase + PCI171X_TIMER_BASE; local 579 i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY); 580 i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY); 583 i8254_write(timer_base, 1, 2, devpriv->divisor2); 584 i8254_write(timer_base, 1, 1, devpriv->divisor1);
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H A D | amplc_pci224.c | 832 unsigned long timer_base = devpriv->iobase1 + PCI224_Z2_CT0; local 846 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 847 i8254_write(timer_base, 0, 2, devpriv->cached_div1); 851 i8254_set_mode(timer_base, 0, 0, I8254_MODE2 | I8254_BINARY); 852 i8254_write(timer_base, 0, 0, devpriv->cached_div2);
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H A D | cb_pcidas.c | 932 unsigned long timer_base = dev->iobase + ADC8254; local 934 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 935 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 937 i8254_write(timer_base, 0, 1, devpriv->divisor1); 938 i8254_write(timer_base, 0, 2, devpriv->divisor2); 1186 unsigned long timer_base = dev->iobase + DAC8254; local 1188 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 1189 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 1191 i8254_write(timer_base, 0, 1, devpriv->ao_divisor1); 1192 i8254_write(timer_base, [all...] |
H A D | das1800.c | 960 unsigned long timer_base = dev->iobase + DAS1800_COUNTER; local 966 i8254_set_mode(timer_base, 0, 1, I8254_MODE2 | I8254_BINARY); 967 i8254_set_mode(timer_base, 0, 2, I8254_MODE2 | I8254_BINARY); 969 i8254_write(timer_base, 0, 1, devpriv->divisor1); 970 i8254_write(timer_base, 0, 2, devpriv->divisor2); 975 i8254_set_mode(timer_base, 0, 0, I8254_MODE0 | I8254_BINARY); 977 i8254_write(timer_base, 0, 0, 1);
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