Searched refs:cache (Results 101 - 125 of 127) sorted by relevance

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/drivers/parisc/
H A Dccio-dma.c3 ** DMA management routines for first generation cache-coherent machines.
50 #include <asm/cache.h> /* for L1_CACHE_BYTES */
486 ** data can avoid this if the mapping covers full cache lines.
/drivers/video/console/
H A Dsticore.c467 "btlb=%d, sysonly=%d, cache=%d, last=%d\n",
472 sti->regions[i].region_desc.cache,
/drivers/net/cris/
H A Deth_v10.c39 #include <asm/cache.h>
142 /* Due to a chip bug we need to flush the cache when descriptors are returned */
331 * avoid cache bug)
1286 * memory (aligned to cache line boundary to avoid bug).
/drivers/net/ethernet/micrel/
H A Dks8851.c22 #include <linux/cache.h>
1534 /* cache the contents of the CCR register for EEPROM, etc. */
H A Dks8851_mll.c31 #include <linux/cache.h>
590 * ks_save_cmd_reg - save the command register from the cache.
603 * ks_restore_cmd_reg - restore the command register from the cache and
/drivers/net/ethernet/sfc/
H A Dtx.c20 #include <linux/cache.h>
150 * read_count (more likely to be a cache miss).
278 * of a cache line, as this is required for write-combining to be
284 * are the size of a cache line.
294 /* Pad the write to the size of a cache line.
509 * the packet, which should be cache-efficient.
/drivers/net/
H A Dmacvlan.c555 .cache = eth_header_cache,
/drivers/pci/
H A Dsetup-bus.c26 #include <linux/cache.h>
/drivers/scsi/csiostor/
H A Dcsio_wr.c40 #include <linux/cache.h>
1327 /* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */
/drivers/net/ethernet/chelsio/cxgb3/
H A Dcxgb3_main.c1031 u16 *cache = phy->phy_cache; local
1063 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1064 *cache++ = be32_to_cpu(p[i]) & 0xffff;
/drivers/firewire/
H A Dnet.c286 .cache = fwnet_header_cache,
/drivers/gpu/drm/radeon/
H A Dci_dpm.c543 u32 cache = 0; local
550 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
566 data |= cache;
579 cache = 0;
/drivers/net/ethernet/broadcom/
H A Dsb1250-mac.c46 #include <asm/cache.h>
48 #include <asm/processor.h> /* Processor type for cache alignment. */
817 * 1. the data does not start in the middle of a cache line.
818 * 2. The data does not end in the middle of a cache line
822 * Remember, the SOCs MAC writes whole cache lines at a time,
824 * data portion starts in the middle of a cache line, the SOC
933 * fill in the descriptor. Note that the number of cache
/drivers/net/ethernet/packetengines/
H A Dhamachi.c164 #include <asm/processor.h> /* Processor type for cache alignment. */
167 #include <asm/cache.h>
395 PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in
491 /* Frequently used and paired value: keep adjacent for cache effect. */
1259 /* Non-x86 Todo: explicitly flush cache lines here. */
/drivers/net/hippi/
H A Drrunner.c45 #include <asm/cache.h>
373 * Why 32 ? is this not cache line size dependent?
/drivers/net/wan/
H A Ddscc4.c96 #include <asm/cache.h>
/drivers/spi/
H A Dspi.c26 #include <linux/cache.h>
/drivers/scsi/aacraid/
H A Daachba.c170 module_param_named(cache, aac_cache, int, S_IRUGO|S_IWUSR);
171 MODULE_PARM_DESC(cache, "Disable Queue Flush commands:\n"
2348 /* Do not cache partition table for arrays */
2377 /* Do not cache partition table for arrays */
2540 /* Issue FIB to tell Firmware to flush it's cache */
/drivers/infiniband/hw/qib/
H A Dqib_iba7322.c2951 * keep mainline interrupt handler cache-friendly
2965 /* keep mainline interrupt handler cache-friendly */
3030 * to improve cache hits for fast path interrupt handling.
6016 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
6025 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
6027 else if (qd->cache.atten[1] >= qib_long_atten &&
6028 QSFP_IS_CU(qd->cache.tech))
7671 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
/drivers/isdn/i4l/
H A Disdn_net.c2009 .cache = isdn_header_cache,
/drivers/net/ethernet/mellanox/mlx4/
H A Dfw.c38 #include <linux/cache.h>
141 [12] = "Large cache line (>64B) CQE stride support",
142 [13] = "Large cache line (>64B) EQE stride support"
/drivers/net/ethernet/realtek/
H A D8139cp.c76 #include <linux/cache.h>
/drivers/net/ethernet/renesas/
H A Dsh_eth.c36 #include <linux/cache.h>
/drivers/net/wireless/ath/ath5k/
H A Dbase.c52 #include <linux/cache.h>
1473 * key cache entry.
1475 * XXX do key cache faulting
2748 * Reset the key cache since some parts do not reset the
3094 * key cache entries can be handled
/drivers/staging/lustre/lnet/klnds/o2iblnd/
H A Do2iblnd.c1430 .cache = !!*kiblnd_tunables.kib_fmr_cache};

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