Searched refs:cache (Results 101 - 125 of 127) sorted by relevance
123456
/drivers/parisc/ |
H A D | ccio-dma.c | 3 ** DMA management routines for first generation cache-coherent machines. 50 #include <asm/cache.h> /* for L1_CACHE_BYTES */ 486 ** data can avoid this if the mapping covers full cache lines.
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/drivers/video/console/ |
H A D | sticore.c | 467 "btlb=%d, sysonly=%d, cache=%d, last=%d\n", 472 sti->regions[i].region_desc.cache,
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/drivers/net/cris/ |
H A D | eth_v10.c | 39 #include <asm/cache.h> 142 /* Due to a chip bug we need to flush the cache when descriptors are returned */ 331 * avoid cache bug) 1286 * memory (aligned to cache line boundary to avoid bug).
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/drivers/net/ethernet/micrel/ |
H A D | ks8851.c | 22 #include <linux/cache.h> 1534 /* cache the contents of the CCR register for EEPROM, etc. */
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H A D | ks8851_mll.c | 31 #include <linux/cache.h> 590 * ks_save_cmd_reg - save the command register from the cache. 603 * ks_restore_cmd_reg - restore the command register from the cache and
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/drivers/net/ethernet/sfc/ |
H A D | tx.c | 20 #include <linux/cache.h> 150 * read_count (more likely to be a cache miss). 278 * of a cache line, as this is required for write-combining to be 284 * are the size of a cache line. 294 /* Pad the write to the size of a cache line. 509 * the packet, which should be cache-efficient.
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/drivers/net/ |
H A D | macvlan.c | 555 .cache = eth_header_cache,
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/drivers/pci/ |
H A D | setup-bus.c | 26 #include <linux/cache.h>
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/drivers/scsi/csiostor/ |
H A D | csio_wr.c | 40 #include <linux/cache.h> 1327 /* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */
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/drivers/net/ethernet/chelsio/cxgb3/ |
H A D | cxgb3_main.c | 1031 u16 *cache = phy->phy_cache; local 1063 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16; 1064 *cache++ = be32_to_cpu(p[i]) & 0xffff;
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/drivers/firewire/ |
H A D | net.c | 286 .cache = fwnet_header_cache,
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/drivers/gpu/drm/radeon/ |
H A D | ci_dpm.c | 543 u32 cache = 0; local 550 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 566 data |= cache; 579 cache = 0;
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/drivers/net/ethernet/broadcom/ |
H A D | sb1250-mac.c | 46 #include <asm/cache.h> 48 #include <asm/processor.h> /* Processor type for cache alignment. */ 817 * 1. the data does not start in the middle of a cache line. 818 * 2. The data does not end in the middle of a cache line 822 * Remember, the SOCs MAC writes whole cache lines at a time, 824 * data portion starts in the middle of a cache line, the SOC 933 * fill in the descriptor. Note that the number of cache
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/drivers/net/ethernet/packetengines/ |
H A D | hamachi.c | 164 #include <asm/processor.h> /* Processor type for cache alignment. */ 167 #include <asm/cache.h> 395 PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in 491 /* Frequently used and paired value: keep adjacent for cache effect. */ 1259 /* Non-x86 Todo: explicitly flush cache lines here. */
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/drivers/net/hippi/ |
H A D | rrunner.c | 45 #include <asm/cache.h> 373 * Why 32 ? is this not cache line size dependent?
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/drivers/net/wan/ |
H A D | dscc4.c | 96 #include <asm/cache.h>
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/drivers/spi/ |
H A D | spi.c | 26 #include <linux/cache.h>
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/drivers/scsi/aacraid/ |
H A D | aachba.c | 170 module_param_named(cache, aac_cache, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(cache, "Disable Queue Flush commands:\n" 2348 /* Do not cache partition table for arrays */ 2377 /* Do not cache partition table for arrays */ 2540 /* Issue FIB to tell Firmware to flush it's cache */
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/drivers/infiniband/hw/qib/ |
H A D | qib_iba7322.c | 2951 * keep mainline interrupt handler cache-friendly 2965 /* keep mainline interrupt handler cache-friendly */ 3030 * to improve cache hits for fast path interrupt handling. 6016 ret = qib_refresh_qsfp_cache(ppd, &qd->cache); 6025 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech)) 6027 else if (qd->cache.atten[1] >= qib_long_atten && 6028 QSFP_IS_CU(qd->cache.tech)) 7671 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
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/drivers/isdn/i4l/ |
H A D | isdn_net.c | 2009 .cache = isdn_header_cache,
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/drivers/net/ethernet/mellanox/mlx4/ |
H A D | fw.c | 38 #include <linux/cache.h> 141 [12] = "Large cache line (>64B) CQE stride support", 142 [13] = "Large cache line (>64B) EQE stride support"
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/drivers/net/ethernet/realtek/ |
H A D | 8139cp.c | 76 #include <linux/cache.h>
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/drivers/net/ethernet/renesas/ |
H A D | sh_eth.c | 36 #include <linux/cache.h>
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/drivers/net/wireless/ath/ath5k/ |
H A D | base.c | 52 #include <linux/cache.h> 1473 * key cache entry. 1475 * XXX do key cache faulting 2748 * Reset the key cache since some parts do not reset the 3094 * key cache entries can be handled
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/drivers/staging/lustre/lnet/klnds/o2iblnd/ |
H A D | o2iblnd.c | 1430 .cache = !!*kiblnd_tunables.kib_fmr_cache};
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