Searched refs:ctrl (Results 201 - 225 of 800) sorted by relevance

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/drivers/isdn/hardware/avm/
H A Db1dma.c451 struct capi_ctr *ctrl = &cinfo->capi_ctrl; local
479 capi_ctr_handle_message(ctrl, ApplId, skb);
499 capi_ctr_handle_message(ctrl, ApplId, skb);
531 capi_ctr_resume_output(ctrl);
535 capi_ctr_suspend_output(ctrl);
546 capi_ctr_ready(ctrl);
704 int b1dma_load_firmware(struct capi_ctr *ctrl, capiloaddata *data) argument
706 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata);
753 void b1dma_reset_ctr(struct capi_ctr *ctrl) argument
755 avmctrl_info *cinfo = (avmctrl_info *)(ctrl
770 b1dma_register_appl(struct capi_ctr *ctrl, u16 appl, capi_register_params *rp) argument
807 b1dma_release_appl(struct capi_ctr *ctrl, u16 appl) argument
838 b1dma_send_message(struct capi_ctr *ctrl, struct sk_buff *skb) argument
863 struct capi_ctr *ctrl = m->private; local
[all...]
H A Dc4.c506 struct capi_ctr *ctrl; local
528 ctrl = &card->ctrlinfo[cidx].capi_ctrl;
541 capi_ctr_handle_message(ctrl, ApplId, skb);
552 ctrl = &card->ctrlinfo[cidx].capi_ctrl;
564 capi_ctr_handle_message(ctrl, ApplId, skb);
599 ctrl = &card->ctrlinfo[cidx].capi_ctrl;
600 capi_ctr_resume_output(ctrl);
606 ctrl = &card->ctrlinfo[cidx].capi_ctrl;
607 capi_ctr_suspend_output(ctrl);
621 ctrl
855 c4_load_firmware(struct capi_ctr *ctrl, capiloaddata *data) argument
899 c4_reset_ctr(struct capi_ctr *ctrl) argument
947 c4_register_appl(struct capi_ctr *ctrl, u16 appl, capi_register_params *rp) argument
992 c4_release_appl(struct capi_ctr *ctrl, u16 appl) argument
1028 c4_send_message(struct capi_ctr *ctrl, struct sk_buff *skb) argument
1052 c4_procinfo(struct capi_ctr *ctrl) argument
1070 struct capi_ctr *ctrl = m->private; local
[all...]
/drivers/mtd/onenand/
H A Domap2.c93 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr) argument
95 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
96 msg, state, ctrl, intr);
99 static void wait_warn(char *msg, int state, unsigned int ctrl, argument
102 printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
103 "intr 0x%04x\n", msg, state, ctrl, intr);
111 unsigned int ctrl, ctrl_mask; local
138 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
139 if (ctrl & ONENAND_CTRL_ERROR) {
140 wait_err("controller error", state, ctrl, int
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/drivers/media/tuners/
H A Dmsi001.c382 static int msi001_s_ctrl(struct v4l2_ctrl *ctrl) argument
384 struct msi001 *s = container_of(ctrl->handler, struct msi001, hdl);
390 ctrl->id, ctrl->name, ctrl->val,
391 ctrl->minimum, ctrl->maximum, ctrl->step);
393 switch (ctrl->id) {
411 dev_dbg(&s->spi->dev, "unkown control %d\n", ctrl
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/drivers/media/usb/gspca/
H A Djeilinj.c400 static int sd_s_ctrl(struct v4l2_ctrl *ctrl) argument
403 container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
411 switch (ctrl->id) {
413 setfreq(gspca_dev, ctrl->val);
416 setred(gspca_dev, ctrl->val);
419 setgreen(gspca_dev, ctrl->val);
422 setblue(gspca_dev, ctrl->val);
425 setautogain(gspca_dev, ctrl->val);
428 jpeg_set_qual(sd->jpeg_hdr, ctrl->val);
429 setcamquality(gspca_dev, ctrl
[all...]
H A Dmars.c156 static int mars_s_ctrl(struct v4l2_ctrl *ctrl) argument
159 container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
164 if (ctrl->id == V4L2_CID_ILLUMINATORS_1) {
166 if (ctrl->is_new && ctrl->val)
175 switch (ctrl->id) {
177 setbrightness(gspca_dev, ctrl->val);
180 setcolors(gspca_dev, ctrl->val);
183 setgamma(gspca_dev, ctrl->val);
190 setsharpness(gspca_dev, ctrl
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/drivers/mmc/host/
H A Dsdhci.c265 u8 ctrl; local
267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
268 ctrl |= SDHCI_CTRL_LED;
269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
274 u8 ctrl; local
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl &= ~SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
724 u8 ctrl; local
855 ctrl
1409 u8 ctrl; local
1454 u8 ctrl; local
1736 u16 ctrl; local
1849 u16 ctrl; local
2053 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); local
[all...]
/drivers/usb/dwc2/
H A Dgadget.c531 u32 ctrl; local
557 ctrl = readl(hsotg->regs + epctrl_reg);
559 if (ctrl & DXEPCTL_STALL) {
642 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
643 ctrl |= DXEPCTL_USBACTEP;
651 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
654 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
655 writel(ctrl, hsotg->regs + epctrl_reg);
885 * @ctrl: USB control request
888 struct usb_ctrlrequest *ctrl)
887 s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg, struct usb_ctrlrequest *ctrl) argument
958 s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg, struct usb_ctrlrequest *ctrl) argument
1044 u32 ctrl; local
1079 s3c_hsotg_process_control(struct s3c_hsotg *hsotg, struct usb_ctrlrequest *ctrl) argument
1362 u32 ctrl; local
1802 u32 ctrl; local
2601 u32 ctrl; local
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/drivers/media/usb/pwc/
H A Dpwc-v4l.c40 #define PWC_CID_CUSTOM(ctrl) ((V4L2_CID_USER_BASE | 0xf000) + custom_ ## ctrl)
42 static int pwc_g_volatile_ctrl(struct v4l2_ctrl *ctrl);
43 static int pwc_s_ctrl(struct v4l2_ctrl *ctrl);
527 static int pwc_g_volatile_ctrl(struct v4l2_ctrl *ctrl) argument
530 container_of(ctrl->handler, struct pwc_device, ctrl_handler);
533 switch (ctrl->id) {
594 PWC_ERROR("g_ctrl %s error %d\n", ctrl->name, ret);
778 static int pwc_s_ctrl(struct v4l2_ctrl *ctrl) argument
781 container_of(ctrl
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/drivers/video/fbdev/
H A Djz4740_fb.c359 uint32_t ctrl; local
380 ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
384 ctrl |= JZ_LCD_CTRL_BPP_1;
387 ctrl |= JZ_LCD_CTRL_BPP_2;
390 ctrl |= JZ_LCD_CTRL_BPP_4;
393 ctrl |= JZ_LCD_CTRL_BPP_8;
396 ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */
398 ctrl |= JZ_LCD_CTRL_BPP_15_16;
403 ctrl |= JZ_LCD_CTRL_BPP_18_24;
442 ctrl |
486 uint32_t ctrl; local
505 uint32_t ctrl; local
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/drivers/clocksource/
H A Darm_arch_timer.c141 unsigned long ctrl; local
143 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
144 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
145 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
146 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
185 unsigned long ctrl; local
189 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
190 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
191 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
225 unsigned long ctrl; local
[all...]
/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dnva3.c109 u32 ctrl = nv_rd32(priv, pll + 0); local
112 if (!(ctrl & 0x00000008)) {
113 if (ctrl & 0x00000001) {
345 const u32 ctrl = pll + 0; local
351 bypass = nv_rd32(priv, ctrl) & 0x00000008;
354 nv_mask(priv, ctrl, 0x00000008, 0x00000008);
360 nv_mask(priv, ctrl, 0x00000015, 0x00000015);
361 nv_mask(priv, ctrl, 0x00000010, 0x00000000);
362 if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) {
363 nv_mask(priv, ctrl,
[all...]
/drivers/media/usb/gspca/gl860/
H A Dgl860.c61 static int sd_s_ctrl(struct v4l2_ctrl *ctrl) argument
64 container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
67 switch (ctrl->id) {
69 sd->vcur.brightness = ctrl->val;
72 sd->vcur.contrast = ctrl->val;
75 sd->vcur.saturation = ctrl->val;
78 sd->vcur.hue = ctrl->val;
81 sd->vcur.gamma = ctrl->val;
84 sd->vcur.mirror = ctrl->val;
87 sd->vcur.flip = ctrl
[all...]
/drivers/scsi/
H A Dsgiwd93.c129 hregs->ctrl = HPC3_SCTRL_ACTIVE;
131 hregs->ctrl = HPC3_SCTRL_ACTIVE | HPC3_SCTRL_DIR;
154 hregs->ctrl |= HPC3_SCTRL_FLUSH;
155 while (hregs->ctrl & HPC3_SCTRL_ACTIVE)
158 hregs->ctrl = 0;
170 hregs->ctrl = HPC3_SCTRL_CRESET;
172 hregs->ctrl = 0;
/drivers/staging/comedi/drivers/
H A Dcb_pcidda.c306 unsigned int ctrl; local
311 ctrl = CB_DDA_DA_CTRL_EN | CB_DDA_DA_CTRL_DAC(channel);
316 ctrl |= CB_DDA_DA_CTRL_RANGE10V;
320 ctrl |= CB_DDA_DA_CTRL_RANGE5V;
324 ctrl |= CB_DDA_DA_CTRL_RANGE2V5;
329 ctrl |= CB_DDA_DA_CTRL_UNIP;
331 outw(ctrl, devpriv->daqio + CB_DDA_DA_CTRL_REG);
/drivers/misc/
H A Dad525x_dpot.c129 unsigned ctrl = 0; local
162 ctrl = DPOT_SPI_READ_RDAC;
164 ctrl = DPOT_SPI_READ_EEPROM;
168 return dpot_read_r8d8(dpot, ctrl);
170 return dpot_read_r8d16(dpot, ctrl);
178 unsigned ctrl = 0; local
190 ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
192 return dpot_read_r8d8(dpot, ctrl);
199 ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ?
201 return dpot_read_r8d8(dpot, ctrl);
330 unsigned tmp = 0, ctrl = 0; local
[all...]
/drivers/usb/gadget/function/
H A Df_audio_source.c465 const struct usb_ctrlrequest *ctrl)
468 u16 ep = le16_to_cpu(ctrl->wIndex);
469 u16 len = le16_to_cpu(ctrl->wLength);
470 u16 w_value = le16_to_cpu(ctrl->wValue);
473 ctrl->bRequest, w_value, len, ep);
475 switch (ctrl->bRequest) {
490 const struct usb_ctrlrequest *ctrl)
494 u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
495 u16 len = le16_to_cpu(ctrl->wLength);
496 u16 w_value = le16_to_cpu(ctrl
464 audio_set_endpoint_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) argument
489 audio_get_endpoint_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) argument
523 audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) argument
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/drivers/media/radio/
H A Dradio-si476x.c94 static int si476x_radio_s_ctrl(struct v4l2_ctrl *ctrl);
95 static int si476x_radio_g_volatile_ctrl(struct v4l2_ctrl *ctrl);
847 static int si476x_radio_g_volatile_ctrl(struct v4l2_ctrl *ctrl) argument
850 struct si476x_radio *radio = v4l2_ctrl_handler_to_radio(ctrl->handler);
854 switch (ctrl->id) {
862 ctrl->val = !!SI476X_PHDIV_STATUS_LINK_LOCKED(retval);
881 static int si476x_radio_s_ctrl(struct v4l2_ctrl *ctrl) argument
885 struct si476x_radio *radio = v4l2_ctrl_handler_to_radio(ctrl->handler);
889 switch (ctrl->id) {
894 ctrl
1428 struct v4l2_ctrl *ctrl; local
1446 struct v4l2_ctrl *ctrl; local
[all...]
H A Dradio-keene.c241 static int keene_s_ctrl(struct v4l2_ctrl *ctrl) argument
250 container_of(ctrl->handler, struct keene_device, hdl);
252 switch (ctrl->id) {
254 radio->muted = ctrl->val;
260 radio->pa = (ctrl->val - 71) * 100 / 62;
264 radio->preemph_75_us = ctrl->val == V4L2_PREEMPHASIS_75_uS;
268 radio->tx = db2tx[(ctrl->val - (s32)ctrl->minimum) / (s32)ctrl->step];
/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.c22 uint32_t ctrl = 0; local
25 ctrl |= HDMI_CTRL_ENABLE;
27 ctrl |= HDMI_CTRL_HDMI;
28 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl);
29 ctrl &= ~HDMI_CTRL_HDMI;
31 ctrl |= HDMI_CTRL_HDMI;
34 ctrl = HDMI_CTRL_HDMI;
37 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl);
39 power_on ? "Enable" : "Disable", ctrl);
/drivers/media/i2c/
H A Dsaa7110.c71 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) argument
73 return &container_of(ctrl->handler, struct saa7110, hdl)->sd;
331 static int saa7110_s_ctrl(struct v4l2_ctrl *ctrl) argument
333 struct v4l2_subdev *sd = to_sd(ctrl);
335 switch (ctrl->id) {
337 saa7110_write(sd, 0x19, ctrl->val);
340 saa7110_write(sd, 0x13, ctrl->val);
343 saa7110_write(sd, 0x12, ctrl->val);
346 saa7110_write(sd, 0x07, ctrl->val);
H A Dvpx3220.c60 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) argument
62 return &container_of(ctrl->handler, struct vpx3220, hdl)->sd;
423 static int vpx3220_s_ctrl(struct v4l2_ctrl *ctrl) argument
425 struct v4l2_subdev *sd = to_sd(ctrl);
427 switch (ctrl->id) {
429 vpx3220_write(sd, 0xe6, ctrl->val);
433 vpx3220_write(sd, 0xe7, ctrl->val + 192);
436 vpx3220_fp_write(sd, 0xa0, ctrl->val);
439 vpx3220_fp_write(sd, 0x1c, ctrl->val);
/drivers/media/pci/cx18/
H A Dcx18-dvb.c507 .ctrl = NULL,
509 static struct xc2028_ctrl ctrl = { local
518 fe->ops.tuner_ops.set_config(fe, &ctrl);
539 .ctrl = NULL,
541 static struct xc2028_ctrl ctrl = { local
550 fe->ops.tuner_ops.set_config(fe, &ctrl);
562 .ctrl = NULL,
564 static struct xc2028_ctrl ctrl = { local
573 fe->ops.tuner_ops.set_config(fe, &ctrl);
/drivers/media/usb/gspca/m5602/
H A Dm5602_po1030.c23 static int po1030_s_ctrl(struct v4l2_ctrl *ctrl);
446 static int po1030_s_ctrl(struct v4l2_ctrl *ctrl) argument
449 container_of(ctrl->handler, struct gspca_dev, ctrl_handler);
456 switch (ctrl->id) {
458 err = po1030_set_auto_white_balance(gspca_dev, ctrl->val);
459 if (err || ctrl->val)
470 err = po1030_set_auto_exposure(gspca_dev, ctrl->val);
471 if (err || ctrl->val == V4L2_EXPOSURE_AUTO)
476 err = po1030_set_gain(gspca_dev, ctrl->val);
/drivers/rtc/
H A Drtc-pm8xxx.c36 * @ctrl: base address of control register
45 unsigned int ctrl; member in struct:pm8xxx_rtc_regs
104 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
111 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
142 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
382 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
388 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
397 .ctrl = 0x11d,
407 .ctrl = 0x1e8,
417 .ctrl
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Completed in 553 milliseconds

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