/drivers/video/fbdev/aty/ |
H A D | mach64_gx.c | 80 const union aty_pll *pll, u32 bpp, u32 accel) 123 u32 bpp, union aty_pll *pll) 153 pll->ibm514.m = RGB514_clocks[i].m; 154 pll->ibm514.n = RGB514_clocks[i].n; 161 const union aty_pll *pll) 166 df = pll->ibm514.m >> 6; 167 vco_div_count = pll->ibm514.m & 0x3f; 168 ref_div_count = pll->ibm514.n; 175 const union aty_pll *pll) 185 aty_st_514(0x20, pll 79 aty_set_dac_514(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument 122 aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument 160 aty_pll_514_to_var(const struct fb_info *info, const union aty_pll *pll) argument 174 aty_set_pll_514(const struct fb_info *info, const union aty_pll *pll) argument 204 aty_set_dac_ATI68860_B(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument 287 aty_set_dac_ATT21C498(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument 340 aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument 399 aty_pll_18818_to_var(const struct fb_info *info, const union aty_pll *pll) argument 428 aty_set_pll18818(const struct fb_info *info, const union aty_pll *pll) argument 496 aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument 565 aty_pll_1703_to_var(const struct fb_info *info, const union aty_pll *pll) argument 571 aty_set_pll_1703(const struct fb_info *info, const union aty_pll *pll) argument 612 aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument 684 aty_pll_8398_to_var(const struct fb_info *info, const union aty_pll *pll) argument 690 aty_set_pll_8398(const struct fb_info *info, const union aty_pll *pll) argument 736 aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument 802 aty_pll_408_to_var(const struct fb_info *info, const union aty_pll *pll) argument 808 aty_set_pll_408(const struct fb_info *info, const union aty_pll *pll) argument 883 aty_set_dac_unsupported(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument [all...] |
H A D | atyfb.h | 136 union aty_pll pll; member in struct:atyfb_par 303 const union aty_pll * pll, u32 bpp, u32 accel); 318 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll); 319 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll); 320 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll); 321 void (*get_pll) (const struct fb_info *info, union aty_pll * pll); 322 int (*init_pll) (const struct fb_info * info, union aty_pll * pll); 323 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll); 335 extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
|
/drivers/clk/mxs/ |
H A D | Makefile | 5 obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
|
/drivers/clk/rockchip/ |
H A D | Makefile | 7 obj-y += clk-pll.o
|
/drivers/clk/spear/ |
H A D | Makefile | 5 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
|
/drivers/cpufreq/ |
H A D | cpufreq-nforce2.c | 63 * @pll: PLL value 67 static int nforce2_calc_fsb(int pll) argument 71 mul = (pll >> 8) & 0xff; 72 div = pll & 0xff; 112 * @pll: PLL value 116 static void nforce2_write_pll(int pll) argument 120 /* Set the pll addr. to 0x00 */ 125 pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll); 174 int pll = 0; local 190 pll [all...] |
H A D | cris-artpec3-cpufreq.c | 27 return clk_ctrl.pll ? 200000 : 6000; 40 clk_ctrl.pll = 1; 42 clk_ctrl.pll = 0;
|
H A D | cris-etraxfs-cpufreq.c | 27 return clk_ctrl.pll ? 200000 : 6000; 40 clk_ctrl.pll = 1; 42 clk_ctrl.pll = 0;
|
H A D | s3c24xx-cpufreq.c | 72 cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); 73 cfg->pll.frequency = fclk; 83 unsigned long pll = cfg->pll.frequency; local 85 cfg->freq.fclk = pll; 86 cfg->freq.hclk = pll / cfg->divs.h_divisor; 87 cfg->freq.pclk = pll / cfg->divs.p_divisor; 105 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, 160 struct cpufreq_frequency_table *pll) 172 cpu_new.pll 158 s3c_cpufreq_settarget(struct cpufreq_policy *policy, unsigned int target_freq, struct cpufreq_frequency_table *pll) argument 284 struct cpufreq_frequency_table *pll; local [all...] |
/drivers/video/fbdev/via/ |
H A D | via_clock.c | 36 static inline u32 cle266_encode_pll(struct via_pll_config pll) argument 38 return (pll.multiplier << 8) 39 | (pll.rshift << 6) 40 | pll.divisor; 43 static inline u32 k800_encode_pll(struct via_pll_config pll) argument 45 return ((pll.divisor - 2) << 16) 46 | (pll.rshift << 10) 47 | (pll.multiplier - 2); 50 static inline u32 vx855_encode_pll(struct via_pll_config pll) argument 52 return (pll [all...] |
/drivers/char/ |
H A D | genrtc.c | 270 struct rtc_pll_info pll; local 276 if (get_rtc_pll(&pll)) 279 return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0; 284 if (copy_from_user(&pll, argp, sizeof(pll))) 286 return set_rtc_pll(&pll); 394 struct rtc_pll_info pll; local 442 if (!get_rtc_pll(&pll)) 450 pll [all...] |
/drivers/clk/ |
H A D | clk-nomadik.c | 167 struct clk_pll *pll = to_pll(hw); local 172 if (pll->id == 1) { 177 } else if (pll->id == 2) { 187 struct clk_pll *pll = to_pll(hw); local 192 if (pll->id == 1) { 197 } else if (pll->id == 2) { 206 struct clk_pll *pll = to_pll(hw); local 210 if (pll->id == 1) { 213 } else if (pll->id == 2) { 222 struct clk_pll *pll local 262 struct clk_pll *pll; local [all...] |
H A D | clk-ls1x.c | 34 u32 pll, rate; local 36 pll = __raw_readl(LS1X_CLK_PLL_FREQ); 37 rate = ((12 + (pll & 0x3f)) * 1000000) + 38 ((((pll >> 8) & 0x3ff) * 1000000) >> 10);
|
/drivers/clk/st/ |
H A D | clkgen-pll.c | 260 struct clkgen_pll *pll = to_clkgen_pll(hw); local 261 u32 locked = CLKGEN_READ(pll, locked_status); 268 struct clkgen_pll *pll = to_clkgen_pll(hw); local 269 u32 poweroff = CLKGEN_READ(pll, pdn_status); 276 struct clkgen_pll *pll = to_clkgen_pll(hw); local 284 pdiv = CLKGEN_READ(pll, pdiv); 285 mdiv = CLKGEN_READ(pll, mdiv); 286 ndiv = CLKGEN_READ(pll, ndiv); 303 struct clkgen_pll *pll = to_clkgen_pll(hw); local 310 mdiv = CLKGEN_READ(pll, mdi 327 struct clkgen_pll *pll = to_clkgen_pll(hw); local 349 struct clkgen_pll *pll = to_clkgen_pll(hw); local 398 struct clkgen_pll *pll; local [all...] |
H A D | clkgen-fsyn.c | 405 * struct st_clk_quadfs_pll - A pll which outputs a fixed multiplier of 427 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); local 430 if (pll->lock) 431 spin_lock_irqsave(pll->lock, flags); 436 if (pll->data->reset_present) 437 CLKGEN_WRITE(pll, nreset, 1); 442 if (pll->data->bwfilter_present) 443 CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF); 446 CLKGEN_WRITE(pll, ndiv, pll 468 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); local 489 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); local 508 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); local 571 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); local 622 struct st_clk_quadfs_pll *pll; local [all...] |
/drivers/gpu/drm/radeon/ |
H A D | radeon_display.c | 917 * @pll: information about the PLL 927 void radeon_compute_pll_avivo(struct radeon_pll *pll, argument 935 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? 945 fb_div_min = pll->min_feedback_div; 946 fb_div_max = pll->max_feedback_div; 948 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { 954 if (pll->flags & RADEON_PLL_USE_REF_DIV) 955 ref_div_min = pll->reference_div; 957 ref_div_min = pll->min_ref_div; 959 if (pll 1077 radeon_compute_pll_legacy(struct radeon_pll *pll, uint64_t freq, uint32_t *dot_clock_p, uint32_t *fb_div_p, uint32_t *frac_fb_div_p, uint32_t *ref_div_p, uint32_t *post_div_p) argument [all...] |
/drivers/clk/keystone/ |
H A D | pll.c | 31 * struct clk_pll_data - pll data structure 33 * register of pll controller, else it is in the pll_ctrl0((bit 11-6) 34 * @phy_pllm: Physical address of PLLM in pll controller. Used when 67 * struct clk_pll - Main pll clock 68 * @hw: clk_hw for the pll 81 struct clk_pll *pll = to_clk_pll(hw); local 82 struct clk_pll_data *pll_data = pll->pll_data; 125 struct clk_pll *pll; local 128 pll = kzalloc(sizeof(*pll), GFP_KERNE [all...] |
/drivers/media/pci/bt8xx/ |
H A D | bttv-cards.c | 100 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable 122 module_param_array(pll, int, NULL, 0444); 135 MODULE_PARM_DESC(pll, "specify installed crystal (0=none, 28=28 MHz, 35=35 MHz, 14=14 MHz)"); 402 .pll = PLL_28, 466 .pll = PLL_28, 478 .pll = PLL_28, 491 .pll = PLL_28, 529 .pll = PLL_28, 544 .pll = PLL_28, 572 .pll [all...] |
/drivers/video/fbdev/matrox/ |
H A D | matroxfb_misc.c | 128 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, argument 132 unsigned int fxtal = pll->ref_freq; 141 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); 142 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); 144 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); 145 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); 146 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); 147 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); 148 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); 151 for (p = 1; p <= pll [all...] |
/drivers/clk/tegra/ |
H A D | Makefile | 6 obj-y += clk-pll.o 7 obj-y += clk-pll-out.o
|
/drivers/clk/at91/ |
H A D | Makefile | 6 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
|
/drivers/clk/qcom/ |
H A D | clk-pll.h | 83 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, 85 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
|
/drivers/gpu/drm/nouveau/core/subdev/devinit/ |
H A D | priv.h | 5 #include <subdev/bios/pll.h> 6 #include <subdev/clock/pll.h>
|
/drivers/gpu/drm/nouveau/core/subdev/clock/ |
H A D | nva3.c | 28 #include <subdev/bios/pll.h> 31 #include "pll.h" 107 read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) argument 109 u32 ctrl = nv_rd32(priv, pll + 0); 114 u32 coef = nv_rd32(priv, pll + 4); 122 if ((pll & 0x00ff00) == 0x00e800) 226 nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, argument 235 info->pll = 0; 241 if (!pll || (diff >= -2000 && diff < 3000)) { 246 ret = nvbios_pll_parse(bios, pll, 266 calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, int clk, u32 pll, int idx) argument 340 prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) argument [all...] |
/drivers/gpu/drm/nouveau/core/subdev/fb/ |
H A D | ramnv40.c | 27 #include <subdev/bios/pll.h> 30 #include <subdev/clock/pll.h> 42 struct nvbios_pll pll; local 46 ret = nvbios_pll_parse(bios, 0x04, &pll); 48 nv_error(pfb, "mclk pll data not found\n"); 52 ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq, 58 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
|