/drivers/media/i2c/smiapp/ |
H A D | smiapp-core.c | 204 struct smiapp_pll *pll = &sensor->pll; local 208 sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt_pix_clk_div); 213 sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt_sys_clk_div); 218 sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div); 223 sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier); 230 DIV_ROUND_UP(pll->op_sys_clk_freq_hz, 1000000 / 256 / 256)); 235 sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op_pix_clk_div); 240 sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op_sys_clk_div); 277 struct smiapp_pll *pll local 2404 struct smiapp_pll *pll = &sensor->pll; local [all...] |
/drivers/video/fbdev/intelfb/ |
H A D | intelfbhw.c | 667 struct pll_min_max *pll = &plls[index]; local 672 vco = pll->ref_clk * m / n; 883 struct pll_min_max *pll = &plls[index]; local 886 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) { 887 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) { 904 struct pll_min_max *pll = &plls[index]; local 921 if (p % 4 == 0 && p1 < pll->min_p1) { 925 if (p1 < pll 943 struct pll_min_max *pll = &plls[index]; local [all...] |
/drivers/video/fbdev/omap2/dss/ |
H A D | hdmi4.c | 46 struct hdmi_pll_data pll; member in struct:__anon7185 201 hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); 204 r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); 247 hdmi_pll_disable(&hdmi.pll, &hdmi.wp); 265 hdmi_pll_disable(&hdmi.pll, &hdmi.wp); 309 hdmi_pll_dump(&hdmi.pll, s); 694 r = hdmi_pll_init(pdev, &hdmi.pll);
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H A D | hdmi5.c | 51 struct hdmi_pll_data pll; member in struct:__anon7186 214 hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); 222 r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); 265 hdmi_pll_disable(&hdmi.pll, &hdmi.wp); 283 hdmi_pll_disable(&hdmi.pll, &hdmi.wp); 327 hdmi_pll_dump(&hdmi.pll, s); 719 r = hdmi_pll_init(pdev, &hdmi.pll);
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H A D | dss.h | 253 unsigned long pll, void *data); 275 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll, 341 unsigned long pll, unsigned long out_min, 340 dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll, unsigned long out_min, dsi_hsdiv_calc_func func, void *data) argument
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/drivers/video/fbdev/riva/ |
H A D | riva_hw.c | 619 unsigned int M, N, P, pll, MClk; local 621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 622 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 808 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local 810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 811 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 1 1071 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local 1116 unsigned int M, N, P, pll, MClk, NVClk; local [all...] |
/drivers/net/wireless/ath/ath9k/ |
H A D | ar5008_phy.c | 876 u32 pll; local 878 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 881 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 883 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 886 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 888 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 890 return pll; 896 u32 pll; local 898 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 901 pll | [all...] |
H A D | ar9002_phy.c | 453 u32 pll; local 464 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); 465 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); 468 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 470 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 472 return pll;
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H A D | ar9003_phy.c | 523 u32 pll; local 525 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); 528 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); 530 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); 532 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); 534 return pll; 540 u32 pll; local 542 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); 545 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); 547 pll | [all...] |
/drivers/gpu/drm/radeon/ |
H A D | radeon_legacy_crtc.c | 751 struct radeon_pll *pll; local 774 pll = &rdev->clock.p2pll; 776 pll = &rdev->clock.p1pll; 778 pll->flags = RADEON_PLL_LEGACY; 781 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 783 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 795 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 810 pll->flags |= RADEON_PLL_USE_REF_DIV; 818 radeon_compute_pll_legacy(pll, mode->clock, 849 pll_gain = radeon_compute_pll_gain(pll [all...] |
H A D | radeon_legacy_tv.c | 46 /* tv pll setting for 27 mhz ref clk */ 55 /* tv pll setting for 14 mhz ref clk */ 242 struct radeon_pll *pll; local 246 pll = &rdev->clock.p2pll; 248 pll = &rdev->clock.p1pll; 251 *pll_ref_freq = pll->reference_freq; 256 if (pll->reference_freq == 2700) 261 if (pll->reference_freq == 2700) 434 struct radeon_pll *pll; local 438 pll [all...] |
/drivers/clk/ |
H A D | clk-xgene.c | 78 pr_debug("%s pll %s\n", pllclk->name, 90 u32 pll; local 95 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); 103 fvco = parent_rate * (N_DIV_RD(pll) + 4); 110 nref = CLKR_RD(pll) + 1; 111 nout = CLKOD_RD(pll) + 1; 112 nfb = CLKF_RD(pll); 116 pr_debug("%s pll recalc rate %ld parent %ld\n", pllclk->name,
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H A D | clk-si5351.c | 66 struct si5351_hw_data pll[2]; member in struct:si5351_driver_data 344 * Si5351 pll a/b 665 /* multisync can set pll */ 1139 * property silabs,pll-source : <num src>, [<..>] 1140 * allow to selectively set pll source 1142 of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) { 1145 "invalid pll %d on pll-source prop\n", num); 1152 "missing pll-source for pll [all...] |
/drivers/gpu/drm/i915/ |
H A D | intel_display.c | 1068 /* XXX: the dsi pll is shared between MIPI DSI ports */ 1099 struct intel_shared_dpll *pll, 1105 if (WARN (!pll, 1109 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); 1112 pll->name, state_string(state), state_string(cur_state)); 1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); local 1806 if (WARN_ON(pll == NULL)) 1809 WARN_ON(!pll->refcount); 1810 if (pll 1098 assert_shared_dpll(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, bool state) argument 1831 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); local 1861 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); local 3764 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); local 3785 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); local 7214 struct intel_shared_dpll *pll; local 7477 struct intel_shared_dpll *pll; local 7803 struct intel_shared_dpll *pll; local 10986 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; local 11676 ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) argument 11693 ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) argument 11700 ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) argument 11722 ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) argument 13338 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; local 13430 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; local [all...] |
/drivers/video/fbdev/ |
H A D | w100fb.c | 1067 static int w100_pll_adjust(struct w100_pll_info *pll) argument 1091 if (tf80 >= (pll->tfgoal)) { 1097 if (tf20 <= (pll->tfgoal)) 1125 static int w100_pll_calibration(struct w100_pll_info *pll) argument 1129 status = w100_pll_adjust(pll); 1154 static int w100_pll_set_clk(struct w100_pll_info *pll) argument 1169 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M; 1170 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int; 1171 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac; 1172 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll 1192 struct w100_pll_info *pll = par->pll_table; local [all...] |
/drivers/media/dvb-frontends/ |
H A D | mb86a20s.c | 1770 u64 pll; local 1817 pll = (((u64)1) << 34) * state->if_freq; 1818 do_div(pll, 63 * fclk); 1819 pll = (1 << 25) - pll; 1823 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); 1826 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); 1829 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); 1833 __func__, fclk, state->if_freq, (long long)pll); 1835 /* pll [all...] |
H A D | dib0090.c | 2237 const struct dib0090_pll *pll = state->current_pll_table_index; local 2351 pll = dib0090_pll_table; 2353 pll = dib0090_p1g_pll_table; 2358 while (state->rf_request > pll->max_freq) 2359 pll++; 2362 state->current_pll_table_index = pll; 2366 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2; 2372 FBDiv = (VCOF_kHz / pll->topresc / FREF); 2373 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; 2392 if (pll [all...] |
/drivers/video/fbdev/aty/ |
H A D | aty128fb.c | 451 struct aty128_pll pll; member in struct:aty128fb_par 575 * Functions to read from/write to the pll registers 1340 static void aty128_set_pll(struct aty128_pll *pll, argument 1362 div3 |= pll->feedback_divider; 1364 div3 |= post_conv[pll->post_divider] << 16; 1380 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, argument 1402 pll->post_divider = post_dividers[i]; 1414 pll->feedback_divider = round_div(n, d); 1415 pll->vclk = vclk; 1418 "vclk_per: %d\n", pll 1426 aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var) argument 1443 aty128_ddafifo(struct aty128_ddafifo *dsp, const struct aty128_pll *pll, u32 depth, const struct aty128fb_par *par) argument 1578 struct aty128_pll pll; local [all...] |
/drivers/clk/mxs/ |
H A D | clk-imx23.c | 80 static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; 88 ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, enumerator in enum:imx23_clk 120 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); 121 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); 122 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); 123 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); 124 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); 146 clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4); 160 clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", [all...] |
/drivers/bcma/ |
H A D | driver_chipcommon_pmu.c | 336 /* Find the output of the "m" pll divider given pll controls that start with 447 u32 pll; local 454 pll = BCMA_CC_PMU5356_MAINPLL_PLL0; 458 pll = BCMA_CC_PMU5357_MAINPLL_PLL0; 461 pll = BCMA_CC_PMU4716_MAINPLL_PLL0; 465 return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
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/drivers/mfd/ |
H A D | twl6040.c | 319 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; 373 if (pll_id != twl6040->pll) { 402 if (twl6040->pll == pll_id) 483 dev_err(twl6040->dev, "unknown pll id %d\n", pll_id); 490 twl6040->pll = pll_id; 501 return twl6040->pll;
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/drivers/media/i2c/ |
H A D | mt9m032.c | 39 #include "aptina-pll.h" 282 struct aptina_pll pll; local 286 pll.ext_clock = pdata->ext_clock; 287 pll.pix_clock = pdata->pix_clock; 289 ret = aptina_pll_calculate(&client->dev, &limits, &pll); 296 (pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) | 297 ((pll.n - 1) & MT9M032_PLL_CONFIG1_PREDIV_MASK)); 307 reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0)
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H A D | mt9p031.c | 35 #include "aptina-pll.h" 135 struct aptina_pll pll; member in struct:mt9p031 260 mt9p031->pll.ext_clock = pdata->ext_freq; 261 mt9p031->pll.pix_clock = pdata->target_freq; 264 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); 281 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1)); 285 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1);
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/drivers/video/fbdev/matrox/ |
H A D | matroxfb_Ti3026.c | 545 minfo->features.pll.vco_freq_min = 110000; 546 minfo->features.pll.ref_freq = 114545; 547 minfo->features.pll.feed_div_min = 2; 548 minfo->features.pll.feed_div_max = 24; 549 minfo->features.pll.in_div_min = 2; 550 minfo->features.pll.in_div_max = 63; 551 minfo->features.pll.post_shift_max = 3;
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/drivers/gpu/drm/nouveau/core/subdev/devinit/ |
H A D | nv04.c | 129 * stage pll 145 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; local 149 if (oldpll == pll) 173 nv_wr32(devinit, reg, pll); 184 if (ss) /* single stage pll mode */
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