/drivers/irqchip/ |
H A D | irq-orion.c | 42 u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) & 87 gc->reg_base = ioremap(r.start, resource_size(&r)); 88 if (!gc->reg_base) 96 writel(0, gc->reg_base + ORION_IRQ_MASK); 115 u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & 184 gc->reg_base = ioremap(r.start, resource_size(&r)); 185 if (!gc->reg_base) { 198 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK); 199 writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
|
H A D | irq-tb10x.c | 46 irq_reg_writel(val, gc->reg_base + reg); 51 return irq_reg_readl(gc->reg_base + reg); 114 void __iomem *reg_base; local 128 reg_base = ioremap(mem.start, resource_size(&mem)); 129 if (!reg_base) { 155 gc->reg_base = reg_base; 190 iounmap(reg_base);
|
H A D | irq-nvic.c | 92 gc->reg_base = nvic_base + 4 * i; 103 writel_relaxed(~0, gc->reg_base + NVIC_ICER);
|
H A D | irq-atmel-aic-common.c | 196 void __iomem *reg_base; local 203 reg_base = of_iomap(node, 0); 204 if (!reg_base) 229 gc->reg_base = reg_base; 251 iounmap(reg_base);
|
/drivers/video/fbdev/ |
H A D | pxa168fb.c | 291 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); 301 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); 326 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); 338 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); 348 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); 361 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); 373 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; 386 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); 399 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); 425 x = readl(fbi->reg_base [all...] |
H A D | goldfishfb.c | 46 void __iomem *reg_base; member in struct:goldfish_fb 63 status = readl(fb->reg_base + FB_INT_STATUS); 130 writel(fb->rotation, fb->reg_base + FB_SET_ROTATION); 146 fb->reg_base + FB_SET_BASE); 160 writel(1, fb->reg_base + FB_SET_BLANK); 163 writel(0, fb->reg_base + FB_SET_BLANK); 205 fb->reg_base = ioremap(r->start, PAGE_SIZE); 206 if (fb->reg_base == NULL) { 217 width = readl(fb->reg_base + FB_GET_WIDTH); 218 height = readl(fb->reg_base [all...] |
/drivers/watchdog/ |
H A D | s3c2410_wdt.c | 126 void __iomem *reg_base; member in struct:s3c2410_wdt 242 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 252 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 254 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 277 wtcon = readl(wdt->reg_base + S3C2410_WTCON); 291 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); 292 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); 293 writel(wtcon, wdt->reg_base + S3C2410_WTCON); 301 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; 342 wtcon = readl(wdt->reg_base [all...] |
/drivers/usb/musb/ |
H A D | da8xx.c | 149 void __iomem *reg_base = musb->ctrl_base; local 156 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); 159 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, 168 void __iomem *reg_base = musb->ctrl_base; local 170 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, 174 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); 291 void __iomem *reg_base = musb->ctrl_base; local 305 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); 309 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); 325 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_RE 411 void __iomem *reg_base = musb->ctrl_base; local [all...] |
H A D | am35x.c | 99 void __iomem *reg_base = musb->ctrl_base; local 106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); 107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); 110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, 119 void __iomem *reg_base = musb->ctrl_base; local 121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); 122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, 125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); 219 void __iomem *reg_base = musb->ctrl_base; local 231 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_RE 355 void __iomem *reg_base = musb->ctrl_base; local [all...] |
/drivers/clk/rockchip/ |
H A D | clk.c | 155 static void __iomem *reg_base; variable 163 reg_base = base; 198 reg_base, list->con_offset, grf_lock_offset, 227 flags, reg_base + list->muxdiv_offset, 235 flags, reg_base + list->muxdiv_offset, 242 reg_base + list->muxdiv_offset, 252 reg_base, list->muxdiv_offset, list->div_flags, 264 reg_base + list->gate_offset, 273 reg_base, list->muxdiv_offset, list->mux_shift, 309 reg_data, rates, nrates, reg_base, [all...] |
/drivers/net/can/sja1000/ |
H A D | sja1000_platform.c | 45 return ioread8(priv->reg_base + reg); 50 iowrite8(val, priv->reg_base + reg); 55 return ioread8(priv->reg_base + reg * 2); 60 iowrite8(val, priv->reg_base + reg * 2); 65 return ioread8(priv->reg_base + reg * 4); 70 iowrite8(val, priv->reg_base + reg * 4); 209 priv->reg_base = addr; 226 dev_info(&pdev->dev, "%s device registered (reg_base=%p, irq=%d)\n", 227 DRV_NAME, priv->reg_base, dev->irq);
|
H A D | sja1000_isa.c | 82 return readb(priv->reg_base + reg); 88 writeb(val, priv->reg_base + reg); 93 return inb((unsigned long)priv->reg_base + reg); 99 outb(val, (unsigned long)priv->reg_base + reg); 105 unsigned long flags, base = (unsigned long)priv->reg_base; 119 unsigned long flags, base = (unsigned long)priv->reg_base; 169 priv->reg_base = base; 174 priv->reg_base = (void __iomem *)port[idx]; 219 dev_info(&pdev->dev, "%s device registered (reg_base=0x%p, irq=%d)\n", 220 DRV_NAME, priv->reg_base, de [all...] |
H A D | peak_pci.c | 150 void __iomem *reg_base; /* first channel base address */ member in struct:peak_pciec_card 405 int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; 460 card->reg_base = priv->reg_base; 533 return readb(priv->reg_base + (port << 2)); 539 writeb(val, priv->reg_base + (port << 2)); 558 void __iomem *cfg_base, *reg_base; local 597 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); 598 if (!reg_base) { 728 void __iomem *reg_base = priv->reg_base; local [all...] |
H A D | tscan1.c | 81 return inb((unsigned long)priv->reg_base + reg); 87 outb(val, (unsigned long)priv->reg_base + reg); 153 priv->reg_base = (void __iomem *)sja1000_base; 186 sja1000_base = (unsigned long)priv->reg_base;
|
H A D | ems_pci.c | 125 return readb(priv->reg_base + (port * 4)); 131 writeb(val, priv->reg_base + (port * 4)); 145 return readb(priv->reg_base + port); 151 writeb(val, priv->reg_base + port); 307 priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET 349 i + 1, priv->reg_base, dev->irq);
|
/drivers/input/keyboard/ |
H A D | nomadik-ske-keypad.c | 57 * @reg_base: ske regsiters base address 65 void __iomem *reg_base; member in struct:ske_keypad 81 ret = readl(keypad->reg_base + addr); 84 writel(ret, keypad->reg_base + addr); 100 while ((readl(keypad->reg_base + SKE_RIS) != 0x00000000) && timeout--) 112 value = readl(keypad->reg_base + SKE_DBCR); 115 writel(value, keypad->reg_base + SKE_DBCR); 156 ske_ris = readl(keypad->reg_base + SKE_RIS); 180 ske_asr = readl(keypad->reg_base + SKE_ASR0 + (4 * i)); 207 while ((readl(keypad->reg_base [all...] |
/drivers/misc/eeprom/ |
H A D | sunxi_sid.c | 39 void __iomem *reg_base; member in struct:sunxi_sid_data 56 sid_key = ioread32be(sid_data->reg_base + round_down(offset, 4)); 118 sid_data->reg_base = devm_ioremap_resource(&pdev->dev, res); 119 if (IS_ERR(sid_data->reg_base)) 120 return PTR_ERR(sid_data->reg_base);
|
/drivers/net/can/cc770/ |
H A D | cc770_isa.c | 122 return readb(priv->reg_base + reg); 128 writeb(val, priv->reg_base + reg); 133 return inb((unsigned long)priv->reg_base + reg); 139 outb(val, (unsigned long)priv->reg_base + reg); 145 unsigned long base = (unsigned long)priv->reg_base; 160 unsigned long base = (unsigned long)priv->reg_base; 211 priv->reg_base = base; 216 priv->reg_base = (void __iomem *)port[idx]; 278 dev_info(&pdev->dev, "device registered (reg_base=0x%p, irq=%d)\n", 279 priv->reg_base, de [all...] |
/drivers/dma/ |
H A D | mmp_tdma.c | 125 void __iomem *reg_base; member in struct:mmp_tdma_chan 146 writel(phys, tdmac->reg_base + TDNDPR); 147 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, 148 tdmac->reg_base + TDCR); 154 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); 156 writel(0, tdmac->reg_base + TDIMR); 162 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 163 tdmac->reg_base + TDCR); 169 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 170 tdmac->reg_base [all...] |
/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_dsi.c | 278 void __iomem *reg_base; member in struct:exynos_dsi 353 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG); 440 writel(500, dsi->reg_base + driver_data->plltmr_reg); 462 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); 470 reg = readl(dsi->reg_base + DSIM_STATUS_REG); 500 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); 510 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); 525 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG); 533 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG); 552 writel(reg, dsi->reg_base [all...] |
/drivers/media/rc/img-ir/ |
H A D | img-ir.h | 141 * @reg_base: Iomem base address of IR register block. 150 void __iomem *reg_base; member in struct:img_ir_priv 162 iowrite32(data, priv->reg_base + reg_offs); 168 return ioread32(priv->reg_base + reg_offs);
|
/drivers/staging/media/davinci_vpfe/ |
H A D | dm365_ipipe_hw.c | 75 u32 reg_base; local 85 reg_base = RSZ_EN_A; 89 reg_base = RSZ_EN_B; 94 regw_rsz(rsz_base, params->oper_mode, reg_base + RSZ_MODE); 97 regw_rsz(rsz_base, val, reg_base + RSZ_420); 100 reg_base + RSZ_I_VPS); 102 reg_base + RSZ_I_HPS); 104 reg_base + RSZ_O_VSZ); 106 reg_base + RSZ_O_HSZ); 108 reg_base [all...] |
/drivers/clk/samsung/ |
H A D | clk-s3c2443.c | 51 static void __iomem *reg_base; variable 77 samsung_clk_save(reg_base, s3c2443_save, 85 samsung_clk_restore(reg_base, s3c2443_save, 362 __raw_writel(0x533c2443, reg_base + SWRST); 396 reg_base = base; 399 reg_base = of_iomap(np, 0); 400 if (!reg_base) 404 ctx = samsung_clk_init(np, reg_base, NR_CLKS); 415 ARRAY_SIZE(s3c2416_pll_clks), reg_base); 418 ARRAY_SIZE(s3c2443_pll_clks), reg_base); [all...] |
/drivers/dma/ioat/ |
H A D | dma.c | 67 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); 73 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); 77 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); 84 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); 111 chan->reg_base = device->reg_base + (0x80 * (idx + 1)); 137 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); 144 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); 176 void __iomem *reg_base = ioat->base.reg_base; local 202 void __iomem *reg_base = chan->reg_base; local [all...] |
/drivers/staging/goldfish/ |
H A D | goldfish_audio.c | 37 char __iomem *reg_base; member in struct:goldfish_audio 63 #define AUDIO_READ(data, addr) (readl(data->reg_base + addr)) 64 #define AUDIO_WRITE(data, addr, x) (writel(x, data->reg_base + addr)) 66 (gf_write64((u64)(x), data->reg_base + addr, data->reg_base+addr2)) 287 data->reg_base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE); 288 if (data->reg_base == NULL)
|