Searched refs:tmp (Results 151 - 175 of 1689) sorted by relevance

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/drivers/gpu/drm/radeon/
H A Devergreen.c1197 u32 tmp = 0; local
1222 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
1225 tmp |= FMT_TRUNCATE_EN;
1230 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
1234 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
1242 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
1318 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); local
1322 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
1323 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
1345 tmp
1591 u32 tmp; local
1616 u32 tmp; local
1685 u32 tmp; local
1755 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | local
1848 u32 tmp, buffer_alloc, i; local
1936 u32 tmp = RREG32(MC_SHARED_CHMAP); local
2192 u32 tmp, arb_control3; local
2379 u32 tmp; local
2397 u32 tmp; local
2419 u32 tmp; local
2477 u32 tmp; local
2510 u32 tmp; local
2536 u32 crtc_enabled, tmp, frame_count, blackout; local
2623 u32 tmp, frame_count; local
2713 u32 tmp; local
2926 u32 tmp; local
3010 u32 hdp_host_path_cntl, tmp; local
3569 u32 tmp; local
3658 u32 i, j, tmp; local
3686 u32 tmp; local
3756 u32 tmp; local
3869 u32 tmp, i; local
4250 u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; local
4312 u32 tmp; local
4597 u32 tmp; local
4745 u32 wptr, tmp; local
[all...]
H A Dr100.c159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; local
164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
175 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
350 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; local
354 tmp = RREG32(voltage->gpio.reg);
356 tmp |= voltage->gpio.mask;
358 tmp &= ~(voltage->gpio.mask);
359 WREG32(voltage->gpio.reg, tmp);
363 tmp
448 u32 tmp; local
479 u32 tmp; local
554 u32 tmp; local
653 uint32_t tmp; local
675 uint32_t tmp; local
700 uint32_t tmp = 0; local
730 u32 tmp; local
952 u32 tmp; local
1109 uint32_t tmp; local
1256 u32 tmp; local
1548 uint32_t tmp; local
2463 uint32_t tmp; local
2478 uint32_t tmp; local
2497 uint32_t tmp; local
2525 uint32_t tmp; local
2533 u32 tmp; local
2551 u32 status, tmp; local
2608 u32 tmp; local
2693 uint32_t tmp; local
2862 uint32_t save, tmp; local
2969 uint32_t csq_stat, csq2_stat, tmp; local
3019 uint32_t tmp; local
3629 uint32_t tmp = 0; local
3685 uint32_t tmp = 0; local
3800 u32 tmp; local
3847 u32 tmp; local
3982 u32 tmp; local
[all...]
H A Dr420.c86 unsigned tmp; local
108 tmp = 0;
114 tmp = (0 << 1);
117 tmp = (3 << 1);
120 tmp = (6 << 1);
123 tmp = (7 << 1);
128 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
129 WREG32(R300_GB_TILE_CONFIG, tmp);
135 tmp = RREG32(R300_DST_PIPE_CONFIG);
136 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFI
480 uint32_t tmp; local
[all...]
H A Drv515.c133 uint32_t tmp; local
137 tmp = RREG32_MC(MC_STATUS);
138 if (tmp & MC_STATUS_IDLE) {
154 unsigned pipe_select_current, gb_pipe_select, tmp; local
163 tmp = RREG32(R300_DST_PIPE_CONFIG);
164 pipe_select_current = (tmp >> 2) & 3;
165 tmp = (1 << pipe_select_current) |
167 WREG32_PLL(0x000D, tmp);
180 uint32_t tmp; local
184 tmp
241 uint32_t tmp; local
259 uint32_t tmp; local
298 u32 crtc_enabled, tmp, frame_count, blackout; local
380 u32 tmp, frame_count; local
1239 u32 tmp; local
1276 uint32_t tmp; local
[all...]
H A Drs690.c37 uint32_t tmp; local
41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
70 fixed20_12 tmp; local
79 tmp.full = dfixed_const(100);
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
93 tmp.full = dfixed_const(100);
95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
207 u32 tmp; local
578 u32 tmp; local
[all...]
H A Dr200.c152 uint32_t tmp; local
226 tmp = idx_value & ~(0x7 << 2);
227 tmp |= tile_flags;
228 ib[idx] = tmp + ((u32)reloc->gpu_offset);
298 tmp = idx_value & ~(0x7 << 16);
299 tmp |= tile_flags;
300 ib[idx] = tmp;
421 tmp = (idx_value >> 23) & 0x7;
422 if (tmp == 2 || tmp
[all...]
H A Dsi.c1280 u32 tmp; local
1282 tmp = RREG32(CG_CLKPIN_CNTL_2);
1283 if (tmp & MUX_TCLK_TO_XCLK)
1286 tmp = RREG32(CG_CLKPIN_CNTL);
1287 if (tmp & XTALIN_DIVIDE)
1885 u32 tmp, buffer_alloc, i; local
1902 tmp = 0; /* 1/2 */
1905 tmp = 2; /* whole */
1909 tmp = 0;
1914 DC_LB_MEMORY_CONFIG(tmp));
1941 u32 tmp = RREG32(MC_SHARED_CHMAP); local
2125 u32 tmp, dmif_size = 12288; local
2233 u32 tmp, arb_control3; local
3062 u32 tmp; local
3612 u32 tmp; local
3738 u32 tmp; local
3820 u32 tmp; local
3950 u32 tmp, i; local
3977 u32 tmp; local
3999 u32 tmp, i; local
4100 u32 tmp; local
4164 u32 tmp; local
5092 u32 tmp = RREG32(CP_INT_CNTL_RING0); local
5118 u32 tmp, tmp2; local
5143 u32 tmp = RREG32(UVD_CGC_CTRL); local
5167 u32 tmp; local
5189 u32 tmp; local
5201 u32 tmp; local
5225 u32 tmp; local
5245 u32 mask = 0, tmp, tmp1; local
5270 u32 tmp = 0; local
5302 u32 data, orig, tmp; local
5342 u32 data, orig, tmp = 0; local
5398 u32 orig, data, tmp; local
5753 u32 tmp = RREG32(GRBM_SOFT_RESET); local
5783 u32 tmp; local
5794 u32 tmp; local
5894 u32 tmp; local
6200 u32 tmp; local
6320 u32 wptr, tmp; local
7249 u32 max_lw, current_lw, tmp; local
[all...]
H A Dradeon_legacy_tv.c303 uint32_t tmp; local
312 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
313 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
325 uint32_t tmp;
332 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
333 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
390 uint32_t tmp; local
398 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
399 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
404 tmp
543 uint32_t vert_space, flicker_removal, tmp; local
843 uint32_t tmp; local
[all...]
/drivers/gpu/drm/
H A Ddrm_debugfs.c92 struct drm_info_node *tmp; local
102 tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
103 if (tmp == NULL) {
108 root, tmp, &drm_debugfs_fops);
112 kfree(tmp);
117 tmp->minor = minor;
118 tmp->dent = ent;
119 tmp->info_ent = &files[i];
122 list_add(&tmp->list, &minor->debugfs_list);
195 struct drm_info_node *tmp; local
[all...]
/drivers/gpu/drm/nouveau/core/subdev/i2c/
H A Danx9805.c38 u8 tmp, i; local
48 while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) {
56 if (tmp & 0x70) {
57 nv_error(port, "link training failed: 0x%02x\n", tmp);
72 u8 tmp; local
76 tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04;
77 nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04);
78 nv_wri2cr(mast, chan->ctrl, 0x07, tmp);
95 while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) {
101 if ((tmp
178 u8 seg = 0x00, off = 0x00, tmp; local
[all...]
/drivers/rtc/
H A Drtc-v3020.c191 unsigned char tmp; local
193 tmp = address;
195 chip->ops->write_bit(chip, (tmp & 1));
196 tmp >>= 1;
234 int tmp; local
240 tmp = v3020_get_reg(chip, V3020_SECONDS);
241 dt->tm_sec = bcd2bin(tmp);
242 tmp = v3020_get_reg(chip, V3020_MINUTES);
243 dt->tm_min = bcd2bin(tmp);
244 tmp
[all...]
/drivers/scsi/
H A Dinitio.c797 struct scsi_ctrl_blk *tmp, *prev; local
803 prev = tmp = host->first_pending;
804 while (tmp != NULL) {
805 if (scb == tmp) { /* Unlink this SCB */
806 if (tmp == host->first_pending) {
807 if ((host->first_pending = tmp->next) == NULL)
810 prev->next = tmp->next;
811 if (tmp == host->last_pending)
814 tmp->next = NULL;
817 prev = tmp;
846 struct scsi_ctrl_blk *tmp; local
867 struct scsi_ctrl_blk *tmp, *prev; local
899 struct scsi_ctrl_blk *tmp, *prev; local
937 struct scsi_ctrl_blk *tmp; local
953 struct scsi_ctrl_blk *tmp, *prev; local
2388 struct scsi_ctrl_blk *tmp, *prev; local
2847 struct scsi_ctrl_blk *scb, *tmp, *prev = NULL /* silence gcc */; local
[all...]
/drivers/media/usb/cx231xx/
H A Dcx231xx-avcore.c2210 u32 tmp = 0; local
2226 tmp = le32_to_cpu(*((__le32 *) value));
2231 tmp &= (~PWR_MODE_MASK);
2233 tmp |= PWR_AV_EN;
2234 value[0] = (u8) tmp;
2235 value[1] = (u8) (tmp >> 8);
2236 value[2] = (u8) (tmp >> 16);
2237 value[3] = (u8) (tmp >> 24);
2242 tmp |= PWR_ISO_EN;
2243 value[0] = (u8) tmp;
2439 u32 tmp = 0; local
2466 u32 tmp = 0; local
2491 u32 tmp = 0; local
2655 __le32 tmp; local
[all...]
/drivers/usb/gadget/udc/
H A Dat91_udc.c170 u32 tmp; local
189 tmp = at91_udp_read(udc, AT91_UDP_FRM_NUM);
190 seq_printf(s, "frame %05x:%s%s frame=%d\n", tmp,
191 (tmp & AT91_UDP_FRM_OK) ? " ok" : "",
192 (tmp & AT91_UDP_FRM_ERR) ? " err" : "",
193 (tmp & AT91_UDP_NUM));
195 tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT);
196 seq_printf(s, "glbstate %02x:%s" FOURBITS "\n", tmp,
197 (tmp & AT91_UDP_RMWUPE) ? " rmwupe" : "",
198 (tmp
473 u32 tmp; local
649 u32 tmp; local
1054 u32 tmp; local
1330 u32 tmp; local
[all...]
/drivers/staging/lustre/lustre/mdc/
H A Dmdc_lib.c142 char *tmp; local
169 tmp = req_capsule_client_get(&req->rq_pill, &RMF_NAME);
170 LOGL0(op_data->op_name, op_data->op_namelen, tmp);
173 tmp = req_capsule_client_get(&req->rq_pill, &RMF_EADATA);
174 memcpy(tmp, data, datalen);
216 char *tmp; local
246 tmp = req_capsule_client_get(&req->rq_pill, &RMF_NAME);
247 LOGL0(op_data->op_name, op_data->op_namelen, tmp);
254 tmp = req_capsule_client_get(&req->rq_pill, &RMF_EADATA);
255 memcpy(tmp, lm
383 char *tmp; local
412 char *tmp; local
440 char *tmp; local
492 char *tmp = req_capsule_client_get(&req->rq_pill, &RMF_NAME); local
577 struct list_head *l, *tmp; local
[all...]
/drivers/clk/at91/
H A Dclk-usb.c48 u32 tmp; local
53 tmp = pmc_read(pmc, AT91_PMC_USB);
54 usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT;
79 u32 tmp; local
85 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS;
87 tmp |= AT91_PMC_USBS;
88 pmc_write(pmc, AT91_PMC_USB, tmp);
103 u32 tmp; local
115 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
116 tmp |
227 u32 tmp; local
279 u32 tmp; local
[all...]
H A Dclk-programmable.c102 u32 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)) & ~layout->css_mask; local
105 tmp &= AT91_PMC_CSSMCK_MCK;
109 tmp |= AT91_PMC_CSSMCK_MCK;
116 pmc_write(pmc, AT91_PMC_PCKR(prog->id), tmp | index);
122 u32 tmp; local
128 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
129 ret = tmp & layout->css_mask;
130 if (layout->have_slck_mck && (tmp & AT91_PMC_CSSMCK_MCK) && !ret)
144 u32 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)) & local
159 tmp | (shif
[all...]
/drivers/of/
H A Dirq.c100 const __be32 *tmp, *imap, *imask, dummy_imask[] = { [0 ... MAX_PHANDLE_ARGS] = ~0 }; local
115 tmp = of_get_property(ipar, "#interrupt-cells", NULL);
116 if (tmp != NULL) {
117 intsize = be32_to_cpu(*tmp);
139 tmp = of_get_property(old, "#address-cells", NULL);
143 } while (old && tmp == NULL);
146 addrsize = (tmp == NULL) ? 2 : be32_to_cpu(*tmp);
225 tmp = of_get_property(newpar, "#interrupt-cells", NULL);
226 if (tmp
291 const __be32 *intspec, *tmp, *addr; local
[all...]
/drivers/input/serio/
H A Dolpc_apsp.c113 unsigned int w, tmp; local
120 tmp = readl(priv->base + PJ_RST_INTERRUPT);
121 if (!(tmp & SP_COMMAND_COMPLETE_RESET)) {
137 writel(tmp | SP_COMMAND_COMPLETE_RESET, priv->base + PJ_RST_INTERRUPT);
147 unsigned int tmp; local
151 tmp = readl(priv->base + PJ_INTERRUPT_MASK);
152 writel(tmp & ~INT_0, priv->base + PJ_INTERRUPT_MASK);
161 unsigned int tmp; local
165 tmp = readl(priv->base + PJ_INTERRUPT_MASK);
166 writel(tmp | INT_
[all...]
/drivers/pci/
H A Dpci-label.c175 union acpi_object *obj, *tmp; local
187 tmp = obj->package.elements;
189 tmp[0].type == ACPI_TYPE_INTEGER &&
190 (tmp[1].type == ACPI_TYPE_STRING ||
191 tmp[1].type == ACPI_TYPE_BUFFER)) {
198 scnprintf(buf, PAGE_SIZE, "%llu\n", tmp->integer.value);
200 if (tmp[1].type == ACPI_TYPE_STRING)
202 tmp[1].string.pointer);
203 else if (tmp[1].type == ACPI_TYPE_BUFFER)
204 dsm_label_utf16s_to_utf8s(tmp
[all...]
/drivers/ssb/
H A Ddriver_extif.c88 u32 tmp; local
94 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
95 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;
96 tmp |= DIV_ROUND_UP(120, ns);
97 extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
100 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
101 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;
102 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT;
103 tmp |= DIV_ROUND_UP(120, ns);
104 extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
[all...]
/drivers/net/ethernet/nxp/
H A Dlpc_eth.c450 u32 tmp; local
453 tmp = mac[0] | ((u32)mac[1] << 8);
454 writel(tmp, LPC_ENET_SA2(pldat->net_base));
455 tmp = mac[2] | ((u32)mac[3] << 8);
456 writel(tmp, LPC_ENET_SA1(pldat->net_base));
457 tmp = mac[4] | ((u32)mac[5] << 8);
458 writel(tmp, LPC_ENET_SA0(pldat->net_base));
465 u32 tmp; local
468 tmp = readl(LPC_ENET_SA2(pldat->net_base));
469 mac[0] = tmp
490 u32 tmp; local
635 u32 tmp; local
1037 u32 tmp; local
1316 u32 tmp; local
[all...]
/drivers/usb/serial/
H A Dopticon.c337 struct serial_struct tmp; local
342 memset(&tmp, 0x00, sizeof(tmp));
345 tmp.type = PORT_16550A;
346 tmp.line = port->minor;
347 tmp.port = 0;
348 tmp.irq = 0;
349 tmp.flags = ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ;
350 tmp.xmit_fifo_size = 1024;
351 tmp
[all...]
/drivers/net/irda/
H A Dsh_sir.c222 u32 limit, min = 0xffffffff, tmp; local
236 tmp = freq % SCLK_BASE;
237 if (tmp < min) {
238 min = tmp;
254 u32 min, rerr, tmp; local
298 tmp = rate - (SCLK_BASE * irbc);
299 tmp *= 10000;
301 rerr = tmp / SCLK_BASE;
306 tmp = abs(rate_err_array[i] - rerr);
307 if (min > tmp) {
[all...]
/drivers/md/
H A Ddm-stats.c37 struct dm_stat_percpu tmp; member in struct:dm_stat_shared
580 memset(&shared->tmp, 0, sizeof(shared->tmp));
583 shared->tmp.sectors[READ] += ACCESS_ONCE(p->sectors[READ]);
584 shared->tmp.sectors[WRITE] += ACCESS_ONCE(p->sectors[WRITE]);
585 shared->tmp.ios[READ] += ACCESS_ONCE(p->ios[READ]);
586 shared->tmp.ios[WRITE] += ACCESS_ONCE(p->ios[WRITE]);
587 shared->tmp.merges[READ] += ACCESS_ONCE(p->merges[READ]);
588 shared->tmp.merges[WRITE] += ACCESS_ONCE(p->merges[WRITE]);
589 shared->tmp
[all...]

Completed in 511 milliseconds

1234567891011>>