Searched refs:IE_IRQ1 (Results 1 - 9 of 9) sorted by relevance

/arch/mips/include/asm/sn/sn0/
H A Dip27.h54 #define SRB_DEV1 IE_IRQ1 /* 0x0800 */
/arch/mips/jazz/
H A Dirq.c90 change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
104 } else if (pending & IE_IRQ1) {
/arch/mips/sni/
H A Dpcit.c186 clear_c0_status(IE_IRQ1);
191 set_c0_status(IE_IRQ1);
246 change_c0_status(ST0_IM, IE_IRQ1);
H A Dpcimt.c303 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
/arch/mips/kvm/
H A Dinterrupt.c147 && (kvm_read_c0_guest_status(cop0) & IE_IRQ1)) {
/arch/mips/kernel/
H A Dsmp-bmips.c279 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
408 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
/arch/mips/lantiq/
H A Dirq.c444 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
447 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
/arch/mips/sgi-ip32/
H A Dip32-irq.c423 else if (unlikely(pending & IE_IRQ1))
502 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
/arch/mips/include/asm/
H A Dmipsregs.h276 #define IE_IRQ1 (_ULCAST_(1) << 11) macro

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