/arch/arm/mach-s3c24xx/include/mach/ |
H A D | hardware.h | 17 extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
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/arch/sparc/include/asm/ |
H A D | asmmacro.h | 21 #define RESTORE_ALL b ret_trap_entry; clr %l6;
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H A D | backoff.h | 63 clr tmp; \
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H A D | ns87303.h | 87 unsigned char clr, unsigned char set) 105 value &= ~(reserved[index] | clr); 86 ns87303_modify(unsigned long port, unsigned int index, unsigned char clr, unsigned char set) argument
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H A D | visasm.h | 38 clr %o5; \
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/arch/sparc/lib/ |
H A D | ffs.S | 12 clr %o0 19 clr %o1 /* 2 */ 23 1: clr %o2 29 clr %o3 32 clr %o4 38 clr %o5
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H A D | lshrdi3.S | 13 clr %o4
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H A D | ashldi3.S | 22 clr %o5
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H A D | strncmp_64.S | 29 clr %o0
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H A D | copy_in_user.S | 80 clr %o0 91 clr %o0
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/arch/powerpc/include/asm/ |
H A D | dcr-native.h | 123 unsigned clr, unsigned set) 131 val = (mfdcrx(base_data) & ~clr) | set; 135 val = (__mfdcr(base_data) & ~clr) | set; 149 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ 151 reg, clr, set) 122 __dcri_clrset(int base_addr, int base_data, int reg, unsigned clr, unsigned set) argument
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H A D | pgtable-ppc32.h | 167 unsigned long clr, 181 : "r" (p), "r" (clr), "r" (set), "m" (*p) 185 *p = __pte((old & ~clr) | set); 196 unsigned long clr, 212 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) 216 *p = __pte((old & ~(unsigned long long)clr) | set); 166 pte_update(pte_t *p, unsigned long clr, unsigned long set) argument 195 pte_update(pte_t *p, unsigned long clr, unsigned long set) argument
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/arch/arm/kernel/ |
H A D | irq.c | 82 unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; local 90 clr |= IRQ_NOREQUEST; 92 clr |= IRQ_NOPROBE; 94 clr |= IRQ_NOAUTOEN; 95 /* Order is clear bits in "clr" then set bits in "set" */ 96 irq_modify_status(irq, clr, set & ~clr);
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/arch/mn10300/kernel/ |
H A D | gdb-low.S | 37 clr d0 define 49 clr d0 define 61 clr d0 define 80 clr d0 define 91 clr d0 define 102 clr d0 define
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H A D | mn10300-watchdog-low.S | 56 clr d0 define 57 clr d1 define
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/arch/m68k/math-emu/ |
H A D | fp_util.S | 70 2: clr.l %d0 99 clr.l %d1 | sign defaults to zero 109 clr.l (%a0) 116 clr.l (%a0)+ 117 clr.l (%a0)+ 118 clr.l (%a0) 142 clr.l (%a0) | low lword = 0 236 clr.b (%a0) 274 clr.l %d0 279 clr [all...] |
/arch/mips/kernel/ |
H A D | head.S | 36 .macro setup_c0_status set clr 39 or t0, ST0_CU0|\set|0x1f|\clr 40 xor t0, 0x1f|\clr
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/arch/m68k/ifpsp060/ |
H A D | os.S | 94 clr.l %d1 | return success 101 clr.l %d1 | return success 127 clr.l %d1 | return success 134 clr.l %d1 | return success 151 clr.l %d0 | clear whole longword 152 clr.l %d1 | assume success 187 clr.l %d1 | assume success 188 clr.l %d0 | clear whole longword 223 clr.l %d1 | assume success 245 clr [all...] |
/arch/m68k/ifpsp060/src/ |
H A D | itest.S | 81 clr.l TESTCTR(%a6) 91 clr.l TESTCTR(%a6) 101 clr.l TESTCTR(%a6) 111 clr.l TESTCTR(%a6) 121 clr.l TESTCTR(%a6) 132 clr.l TESTCTR(%a6) 142 clr.l TESTCTR(%a6) 169 clr.l %d1 181 clr.l IREGS+0x8(%a6) 182 clr [all...] |
H A D | ilsp.S | 298 clr.l %d1 313 clr.w %d5 327 clr.l DDNORMAL(%a6) # count of shifts for normalization 328 clr.b DDSECOND(%a6) # clear flag for quotient digits 329 clr.l %d1 # %d1 will hold trial quotient 362 clr.w %d6 # word u3 left 405 clr.l %d2 408 clr.w %d3 # %d3 now ls word of divisor 412 clr.w %d3 # %d3 now ms word of divisor 421 clr [all...] |
/arch/alpha/lib/ |
H A D | clear_user.S | 76 clr $0 # .. e1 : 107 clr $0 # .. e1 :
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/arch/mn10300/lib/ |
H A D | __ashldi3.S | 47 clr d0 define
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H A D | __lshrdi3.S | 48 clr d1 define
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/arch/s390/net/ |
H A D | bpf_jit.S | 39 clr %r11,%r3 # hlen <= offset + 4 ? 64 clr %r11,%r3 # hlen <= offset + 2 ? 89 clr %r11,%r3 # hlen < offset ? 110 clr %r11,%r3 # hlen < offset ?
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/arch/mips/include/asm/octeon/ |
H A D | cvmx-gpio-defs.h | 371 uint64_t clr:24; member in struct:cvmx_gpio_tx_clr::cvmx_gpio_tx_clr_s 373 uint64_t clr:24; 382 uint64_t clr:16; member in struct:cvmx_gpio_tx_clr::cvmx_gpio_tx_clr_cn38xx 384 uint64_t clr:16; 399 uint64_t clr:20; member in struct:cvmx_gpio_tx_clr::cvmx_gpio_tx_clr_cn61xx 401 uint64_t clr:20;
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