| /arch/arm/mach-ep93xx/ |
| H A D | clock.c | 35 void __iomem *enable_reg; member in struct:clk
56 .enable_reg = EP93XX_SYSCON_DEVCFG,
63 .enable_reg = EP93XX_SYSCON_DEVCFG,
70 .enable_reg = EP93XX_SYSCON_DEVCFG,
91 .enable_reg = EP93XX_SYSCON_PWRCNT,
97 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
112 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
119 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
127 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
135 .enable_reg
[all...] |
| /arch/arm/mach-lpc32xx/ |
| H A D | clock.h | 34 void __iomem *enable_reg; member in struct:clk
|
| H A D | clock.c | 547 tmp = __raw_readl(clk->enable_reg);
554 __raw_writel(tmp, clk->enable_reg);
563 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
570 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
577 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
584 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
591 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
598 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
605 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
612 .enable_reg
[all...] |
| /arch/arm/mach-omap2/ |
| H A D | clock3517.c | 55 *idlest_reg = (__force void __iomem *)(clk->enable_reg);
78 *other_reg = (__force void __iomem *)(clk->enable_reg);
107 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
|
| H A D | clock34xx.c | 47 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
85 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
122 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
|
| H A D | cclock3xxx_data.c | 187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
453 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
481 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
526 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
582 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
753 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
767 .enable_reg
[all...] |
| H A D | clkt_iclk.c | 32 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
46 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
|
| H A D | clock.c | 253 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
278 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
300 * if @hw has a null clock enable_reg, or zero upon success.
320 if (unlikely(clk->enable_reg == NULL)) {
321 pr_err("%s: %s missing enable_reg\n", __func__,
328 v = omap2_clk_readl(clk, clk->enable_reg);
333 omap2_clk_writel(v, clk, clk->enable_reg);
334 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
362 if (!clk->enable_reg) {
367 pr_err("%s: independent clock %s has no enable_reg\
[all...] |
| H A D | clock.h | 95 .enable_reg = _enable_reg, \
|
| /arch/arm/mach-omap1/ |
| H A D | clock_data.c | 101 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
113 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
135 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
154 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
165 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
178 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
191 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
237 .enable_reg = DSP_IDLECT2,
249 .enable_reg
[all...] |
| H A D | clock.c | 46 unsigned int val = __raw_readl(clk->enable_reg);
334 val = __raw_readl(clk->enable_reg);
341 __raw_writel(val, clk->enable_reg);
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
361 __raw_writew(ratio_bits, clk->enable_reg);
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1;
401 __raw_writew(ratio_bits, clk->enable_reg);
457 if (unlikely(clk->enable_reg == NULL)) {
464 regval32 = __raw_readl(clk->enable_reg);
466 __raw_writel(regval32, clk->enable_reg);
[all...] |
| H A D | clock.h | 109 * @enable_reg: register to write to enable the clock (see @enable_bit)
114 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
149 void __iomem *enable_reg; member in struct:clk
|
| /arch/arm/mach-shmobile/ |
| H A D | clock-r8a73a4.c | 178 .enable_reg = (void __iomem *)reg, \
249 frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
303 void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
323 .enable_reg = (void __iomem *)FRQCRB,
338 .enable_reg = (void __iomem *)FRQCRB,
456 .enable_reg = (void __iomem *)_reg, \
|
| H A D | clock-sh73a0.c | 103 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
108 if (__raw_readl(clk->enable_reg) & (1 << 20))
124 .enable_reg = (void __iomem *)PLL0CR,
132 .enable_reg = (void __iomem *)PLL1CR,
140 .enable_reg = (void __iomem *)PLL2CR,
148 .enable_reg = (void __iomem *)PLL3CR,
|
| H A D | clock-r8a7740.c | 132 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
145 .enable_reg = (void __iomem *)FRQCRC,
152 .enable_reg = (void __iomem *)FRQCRA,
|
| H A D | clock-sh7372.c | 100 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
113 .enable_reg = (void __iomem *)FRQCRC,
120 .enable_reg = (void __iomem *)FRQCRA,
|
| /arch/arm/plat-omap/ |
| H A D | dma.c | 1223 u32 val, enable_reg; local
1232 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1233 val &= enable_reg; /* Dispatch only relevant interrupts */
|
| /arch/sh/drivers/pci/ |
| H A D | pcie-sh7786.c | 239 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);
|