Searched refs:BACKLIGHT_DUTY_CYCLE_MASK (Results 1 - 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/
H A Dintel_panel.c488 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
496 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
506 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
524 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
557 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
567 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
589 mask = BACKLIGHT_DUTY_CYCLE_MASK;
606 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
1249 if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK)
1252 cur_val &= BACKLIGHT_DUTY_CYCLE_MASK;
[all...]
H A Di915_reg.h3002 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) macro
/drivers/gpu/drm/gma500/
H A Dpsb_intel_lvds.c202 blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
211 ~BACKLIGHT_DUTY_CYCLE_MASK;
286 BACKLIGHT_DUTY_CYCLE_MASK);
449 BACKLIGHT_DUTY_CYCLE_MASK);
H A Dcdv_intel_lvds.c183 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
190 ~BACKLIGHT_DUTY_CYCLE_MASK;
333 BACKLIGHT_DUTY_CYCLE_MASK);
H A Dcdv_device.c109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
H A Doaktrail_lvds.c176 BACKLIGHT_DUTY_CYCLE_MASK);
H A Dpsb_intel_reg.h116 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) macro

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