Searched refs:BLC_PWM_CTL2 (Results 1 - 8 of 8) sorted by relevance

/drivers/gpu/drm/gma500/
H A Doaktrail_device.c94 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
135 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
247 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
371 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
H A Dcdv_device.c86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
290 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
358 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
H A Dcdv_intel_lvds.c766 pwm = REG_READ(BLC_PWM_CTL2);
772 REG_WRITE(BLC_PWM_CTL2, pwm);
H A Dcdv_intel_dp.c1882 pwm_ctrl = REG_READ(BLC_PWM_CTL2);
1884 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
H A Dpsb_intel_reg.h93 #define BLC_PWM_CTL2 0x61250 macro
/drivers/gpu/drm/i915/
H A Dintel_panel.c712 tmp = I915_READ(BLC_PWM_CTL2);
713 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE);
878 ctl2 = I915_READ(BLC_PWM_CTL2);
882 I915_WRITE(BLC_PWM_CTL2, ctl2);
897 I915_WRITE(BLC_PWM_CTL2, ctl2);
898 POSTING_READ(BLC_PWM_CTL2);
899 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
1214 ctl2 = I915_READ(BLC_PWM_CTL2);
H A Di915_ums.c286 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
314 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
H A Di915_reg.h2961 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ macro

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