Searched refs:BLC_PWM_CTL2 (Results 1 - 8 of 8) sorted by relevance
/drivers/gpu/drm/gma500/ |
H A D | oaktrail_device.c | 94 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 135 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 247 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 371 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
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H A D | cdv_device.c | 86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 290 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); 358 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
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H A D | cdv_intel_lvds.c | 766 pwm = REG_READ(BLC_PWM_CTL2); 772 REG_WRITE(BLC_PWM_CTL2, pwm);
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H A D | cdv_intel_dp.c | 1882 pwm_ctrl = REG_READ(BLC_PWM_CTL2); 1884 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
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H A D | psb_intel_reg.h | 93 #define BLC_PWM_CTL2 0x61250 macro
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/drivers/gpu/drm/i915/ |
H A D | intel_panel.c | 712 tmp = I915_READ(BLC_PWM_CTL2); 713 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); 878 ctl2 = I915_READ(BLC_PWM_CTL2); 882 I915_WRITE(BLC_PWM_CTL2, ctl2); 897 I915_WRITE(BLC_PWM_CTL2, ctl2); 898 POSTING_READ(BLC_PWM_CTL2); 899 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); 1214 ctl2 = I915_READ(BLC_PWM_CTL2);
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H A D | i915_ums.c | 286 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); 314 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
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H A D | i915_reg.h | 2961 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ macro
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