Searched refs:GENERAL_PWRMGT (Results 1 - 25 of 25) sorted by relevance

/drivers/gpu/drm/radeon/
H A Drv730d.h66 #define GENERAL_PWRMGT 0x63c macro
H A Drv770_dpm.c171 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
186 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
198 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
207 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
217 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
219 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
224 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
773 WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN, ~BACKBIAS_PAD_EN);
775 WREG32_P(GENERAL_PWRMGT, 0, ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN));
785 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_E
[all...]
H A Dbtcd.h29 #define GENERAL_PWRMGT 0x63c macro
H A Drv6xxd.h30 #define GENERAL_PWRMGT 0x618 macro
H A Dtrinityd.h172 #define GENERAL_PWRMGT 0x670 macro
H A Drv6xx_dpm.c365 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
367 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
1174 WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,
1177 WREG32_P(GENERAL_PWRMGT, 0,
1213 WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1225 WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1238 WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
1240 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
1259 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
1261 WREG32_P(GENERAL_PWRMGT,
[all...]
H A Dr600_dpm.c266 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
268 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
274 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
276 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
281 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
287 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
289 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
294 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
H A Drv730_dpm.c457 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
469 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
H A Dsumod.h149 #define GENERAL_PWRMGT 0x63c macro
H A Dci_dpm.c989 tmp = RREG32_SMC(GENERAL_PWRMGT);
994 WREG32_SMC(GENERAL_PWRMGT, tmp);
996 tmp = RREG32_SMC(GENERAL_PWRMGT);
998 WREG32_SMC(GENERAL_PWRMGT, tmp);
1106 tmp = RREG32_SMC(GENERAL_PWRMGT);
1108 WREG32_SMC(GENERAL_PWRMGT, tmp);
1167 tmp = RREG32_SMC(GENERAL_PWRMGT);
1169 WREG32_SMC(GENERAL_PWRMGT, tmp);
1457 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1463 WREG32_SMC(GENERAL_PWRMGT, tm
[all...]
H A Dcypress_dpm.c92 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
94 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
227 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
233 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
241 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
1576 u32 tmp = RREG32(GENERAL_PWRMGT);
H A Dsi_dpm.c3198 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3200 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3225 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3230 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3472 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3474 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3479 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3612 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3615 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
5593 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_E
[all...]
H A Dnid.h570 #define GENERAL_PWRMGT 0x63c macro
H A Drs600d.h652 #define GENERAL_PWRMGT 0x8 macro
H A Drv770d.h139 #define GENERAL_PWRMGT 0x63c macro
H A Dni_dpm.c1021 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3503 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
3505 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
H A Dcikd.h89 #define GENERAL_PWRMGT 0xC0200000 macro
H A Dsid.h202 #define GENERAL_PWRMGT 0x780 macro
H A Dbtc_dpm.c1381 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
1383 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
H A Dkv_dpm.c645 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
648 WREG32_SMC(GENERAL_PWRMGT, tmp);
H A Devergreend.h119 #define GENERAL_PWRMGT 0x63c macro
H A Dr600d.h1290 #define GENERAL_PWRMGT 0x618 macro
H A Dsumo_dpm.c776 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
H A Dtrinity_dpm.c760 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
H A Dcik.c1655 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)

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