Searched refs:PFIT_CONTROL (Results 1 - 17 of 17) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| H A D | oaktrail_lvds.c | 141 REG_WRITE(PFIT_CONTROL, 0);
147 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
151 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
154 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
157 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
159 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
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| H A D | psb_intel_lvds.c | 281 lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
322 REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL);
499 REG_WRITE(PFIT_CONTROL, pfit_control);
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| H A D | mdfld_device.c | 221 regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
349 PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL);
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| H A D | cdv_device.c | 293 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
360 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
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| H A D | oaktrail_crtc.c | 356 pfit_control = REG_READ(PFIT_CONTROL);
427 REG_WRITE(PFIT_CONTROL, 0);
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| H A D | oaktrail_device.c | 249 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
373 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
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| H A D | psb_intel_display.c | 92 pfit_control = REG_READ(PFIT_CONTROL);
218 REG_WRITE(PFIT_CONTROL, 0);
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| H A D | cdv_intel_display.c | 570 pfit_control = REG_READ(PFIT_CONTROL);
776 REG_WRITE(PFIT_CONTROL, 0);
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| H A D | mdfld_intel_display.c | 115 pfit_control = REG_READ(PFIT_CONTROL);
770 REG_WRITE(PFIT_CONTROL, 0);
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| H A D | cdv_intel_lvds.c | 386 REG_WRITE(PFIT_CONTROL, pfit_control);
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| H A D | psb_intel_reg.h | 217 #define PFIT_CONTROL 0x61230 macro
849 /* #define PFIT_CONTROL 0x61230 */
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| H A D | cdv_intel_dp.c | 908 REG_WRITE(PFIT_CONTROL, pfit_control);
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| /drivers/gpu/drm/i915/ |
| H A D | i915_suspend.c | 227 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
268 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
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| H A D | intel_overlay.c | 849 u32 pfit_control = I915_READ(PFIT_CONTROL);
1022 pfit_control = I915_READ(PFIT_CONTROL);
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| H A D | intel_lvds.c | 122 tmp = I915_READ(PFIT_CONTROL);
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| H A D | intel_display.c | 4429 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4433 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4920 I915_READ(PFIT_CONTROL));
4921 I915_WRITE(PFIT_CONTROL, 0);
6287 tmp = I915_READ(PFIT_CONTROL);
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| H A D | i915_reg.h | 2913 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) macro
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