Searched refs:PP_CONTROL (Results 1 - 12 of 12) sorted by relevance

/drivers/gpu/drm/gma500/
H A Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON);
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON);
H A Dpsb_intel_lvds.c232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
277 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL);
328 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL);
332 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
338 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL)
[all...]
H A Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
H A Dcdv_intel_dp.c196 pp = REG_READ(PP_CONTROL);
199 REG_WRITE(PP_CONTROL, pp);
200 REG_READ(PP_CONTROL);
210 pp = REG_READ(PP_CONTROL);
213 REG_WRITE(PP_CONTROL, pp);
214 REG_READ(PP_CONTROL);
229 pp = REG_READ(PP_CONTROL);
233 REG_WRITE(PP_CONTROL, pp);
234 REG_READ(PP_CONTROL);
254 pp = REG_READ(PP_CONTROL);
[all...]
H A Dcdv_intel_lvds.c209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
H A Doaktrail_device.c243 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
272 PSB_WVDC32(0, PP_CONTROL);
380 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
H A Dcdv_device.c287 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
366 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
H A Dpsb_intel_reg.h180 #define PP_CONTROL 0x61204 macro
846 /* #define PP_CONTROL 0x61204 */
/drivers/gpu/drm/i915/
H A Di915_suspend.c211 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
219 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
288 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
H A Dintel_lvds.c223 ctl_reg = PP_CONTROL;
250 ctl_reg = PP_CONTROL;
910 I915_WRITE(PP_CONTROL,
911 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
H A Di915_reg.h2906 #define PP_CONTROL 0x61204 macro
H A Dintel_display.c1219 pp_reg = PP_CONTROL;

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