Searched refs:PP_ON (Results 1 - 10 of 10) sorted by relevance

/drivers/gpu/drm/gma500/
H A Dpsb_lid.c43 } while ((pp_status & PP_ON) == 0 &&
46 if (REG_READ(PP_STATUS) & PP_ON) {
59 } while ((pp_status & PP_ON) == 0);
H A Dpsb_intel_lvds.c236 } while ((pp_status & PP_ON) == 0);
247 } while (pp_status & PP_ON);
336 } while ((pp_status & PP_ON) == 0);
342 } while (pp_status & PP_ON);
H A Doaktrail_lvds.c60 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
71 } while (pp_status & PP_ON);
H A Dcdv_intel_lvds.c213 } while ((pp_status & PP_ON) == 0);
224 } while (pp_status & PP_ON);
H A Dcdv_intel_dp.c223 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;
249 u32 pp, idle_off_mask = PP_ON ;
H A Dpsb_intel_reg.h163 # define PP_ON (1 << 31) macro
/drivers/gpu/drm/i915/
H A Dintel_lvds.c231 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
257 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
H A Dintel_dp.c384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1259 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1260 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1262 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1265 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
4808 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
H A Di915_reg.h2881 #define PP_ON (1 << 31) macro
H A Dintel_display.c7533 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");

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