Searched refs:SCLK_PWRMGT_CNTL (Results 1 - 19 of 19) sorted by relevance

/drivers/gpu/drm/radeon/
H A Drv730d.h83 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Drv770_dpm.c134 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
136 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
137 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
138 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
173 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN)
177 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
182 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
200 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
852 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
854 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SE
[all...]
H A Dtrinityd.h175 #define SCLK_PWRMGT_CNTL 0x678 macro
H A Dr600_dpm.c244 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
246 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
303 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
305 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
358 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
360 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
362 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
364 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
H A Dcypress_dpm.c103 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
104 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
105 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
141 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
143 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
145 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
146 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
147 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
151 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
248 WREG32_P(SCLK_PWRMGT_CNTL,
[all...]
H A Dsumo_dpm.c92 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
94 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
95 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
96 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
442 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
444 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
450 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
918 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
923 WREG32_P(SCLK_PWRMGT_CNTL,
[all...]
H A Dtrinity_dpm.c444 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
446 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
447 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
448 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
507 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
509 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN);
771 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)
802 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
807 WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,
H A Drv730_dpm.c453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
471 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
H A Dsumod.h152 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dci_dpm.c1110 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1112 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1171 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1173 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1194 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1200 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1611 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1613 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1629 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1631 WREG32_SMC(SCLK_PWRMGT_CNTL, tm
[all...]
H A Dkv_dpm.c660 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
665 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
670 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
674 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
H A Dnid.h588 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Drv770d.h158 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dsi_dpm.c3236 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3238 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3657 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3659 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3662 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3665 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
H A Dni_dpm.c1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1206 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1207 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
H A Dcikd.h109 #define SCLK_PWRMGT_CNTL 0xC0200008 macro
H A Dsid.h213 #define SCLK_PWRMGT_CNTL 0x788 macro
H A Devergreend.h137 #define SCLK_PWRMGT_CNTL 0x644 macro
H A Dr600d.h1307 #define SCLK_PWRMGT_CNTL 0x620 macro

Completed in 668 milliseconds