Searched refs:clk_pll (Results 1 - 19 of 19) sorted by relevance

/drivers/clk/mxs/
H A Dclk-pll.c21 * struct clk_pll - mxs pll clock
30 struct clk_pll { struct
37 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
41 struct clk_pll *pll = to_clk_pll(hw);
52 struct clk_pll *pll = to_clk_pll(hw);
59 struct clk_pll *pll = to_clk_pll(hw);
68 struct clk_pll *pll = to_clk_pll(hw);
76 struct clk_pll *pll = to_clk_pll(hw);
92 struct clk_pll *pll;
/drivers/clk/qcom/
H A Dclk-pll.h36 * struct clk_pll - phase locked loop (PLL)
47 struct clk_pll { struct
66 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
83 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
85 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
H A Dclk-pll.c39 struct clk_pll *pll = to_clk_pll(hw);
84 struct clk_pll *pll = to_clk_pll(hw);
99 struct clk_pll *pll = to_clk_pll(hw);
146 struct clk_pll *pll = to_clk_pll(hw);
159 struct clk_pll *pll = to_clk_pll(hw);
195 static int wait_for_pll(struct clk_pll *pll)
219 struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk)));
235 clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
254 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
281 void clk_pll_configure_sr(struct clk_pll *pl
[all...]
H A Dgcc-ipq806x.c35 static struct clk_pll pll0 = {
62 static struct clk_pll pll3 = {
78 static struct clk_pll pll8 = {
105 static struct clk_pll pll14 = {
H A Dmmcc-msm8974.c186 static struct clk_pll mmpll0 = {
213 static struct clk_pll mmpll1 = {
240 static struct clk_pll mmpll2 = {
255 static struct clk_pll mmpll3 = {
H A Dmmcc-apq8084.c221 static struct clk_pll mmpll0 = {
248 static struct clk_pll mmpll1 = {
275 static struct clk_pll mmpll2 = {
290 static struct clk_pll mmpll3 = {
306 static struct clk_pll mmpll4 = {
H A Dgcc-apq8084.c108 static struct clk_pll gpll0 = {
171 static struct clk_pll gpll1 = {
198 static struct clk_pll gpll4 = {
H A Dgcc-msm8960.c35 static struct clk_pll pll3 = {
51 static struct clk_pll pll8 = {
78 static struct clk_pll pll14 = {
H A Dgcc-msm8974.c64 static struct clk_pll gpll0 = {
127 static struct clk_pll gpll1 = {
154 static struct clk_pll gpll4 = {
H A Dmmcc-msm8960.c84 static struct clk_pll pll2 = {
100 static struct clk_pll pll15 = {
H A Dgcc-msm8660.c35 static struct clk_pll pll8 = {
/drivers/clk/at91/
H A Dclk-pll.c57 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
59 struct clk_pll { struct
74 struct clk_pll *pll = (struct clk_pll *)dev_id;
84 struct clk_pll *pll = to_clk_pll(hw);
132 struct clk_pll *pll = to_clk_pll(hw);
141 struct clk_pll *pll = to_clk_pll(hw);
153 struct clk_pll *pll = to_clk_pll(hw);
161 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
266 struct clk_pll *pl
[all...]
/drivers/clk/keystone/
H A Dpll.c67 * struct clk_pll - Main pll clock
71 struct clk_pll { struct
76 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
81 struct clk_pll *pll = to_clk_pll(hw);
125 struct clk_pll *pll;
/drivers/clk/
H A Dclk-nomadik.c143 struct clk_pll { struct
162 #define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
167 struct clk_pll *pll = to_pll(hw);
187 struct clk_pll *pll = to_pll(hw);
206 struct clk_pll *pll = to_pll(hw);
222 struct clk_pll *pll = to_pll(hw);
262 struct clk_pll *pll;
H A Dclk-vt8500.c50 struct clk_pll { struct
316 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
542 struct clk_pll *pll = to_clk_pll(hw);
585 struct clk_pll *pll = to_clk_pll(hw);
616 struct clk_pll *pll = to_clk_pll(hw);
654 struct clk_pll *pll_clk;
/drivers/clk/spear/
H A Dclk-vco-pll.c66 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
87 struct clk_pll *pll = to_clk_pll(hw);
127 struct clk_pll *pll = to_clk_pll(hw);
147 struct clk_pll *pll = to_clk_pll(hw);
283 struct clk_pll *pll;
H A Dclk.h102 struct clk_pll { struct
/drivers/staging/imx-drm/
H A Dimx-ldb.c83 struct clk *clk_pll[2]; /* upstream clock we can adjust */ member in struct:imx_ldb
145 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
146 clk_set_rate(ldb->clk_pll[chno], serial_clk);
149 clk_get_rate(ldb->clk_pll[chno]));
345 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
347 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
/drivers/clk/sirf/
H A Dclk-common.c32 struct clk_pll { struct
37 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
76 struct clk_pll *clk = to_pllclk(hw);
128 struct clk_pll *clk = to_pllclk(hw);
216 static struct clk_pll clk_pll1 = {
223 static struct clk_pll clk_pll2 = {
230 static struct clk_pll clk_pll3 = {

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