Searched refs:cstate (Results 1 - 25 of 28) sorted by relevance

12

/drivers/net/wireless/rtlwifi/rtl8723ae/
H A Dhal_bt_coexist.c47 rtlpriv->btcoexist.cstate &=
51 rtlpriv->btcoexist.cstate |=
54 rtlpriv->btcoexist.cstate &=
58 rtlpriv->btcoexist.cstate |=
61 rtlpriv->btcoexist.cstate &=
64 rtlpriv->btcoexist.cstate |= BT_COEX_STATE_WIFI_IDLE;
65 rtlpriv->btcoexist.cstate &=
67 rtlpriv->btcoexist.cstate &=
73 rtlpriv->btcoexist.cstate |=
75 rtlpriv->btcoexist.cstate
[all...]
H A Dhal_btc.c46 rtlpriv->btcoexist.cstate = 0;
137 rtlpriv->btcoexist.cstate |=
142 rtlpriv->btcoexist.cstate &= ~BT_COEX_STATE_DEC_BT_POWER;
151 rtlpriv->btcoexist.cstate) &&
366 rtlpriv->btcoexist.cstate |=
1387 rtlpriv->btcoexist.cstate |=
1406 rtlpriv->btcoexist.cstate &=
1416 rtlpriv->btcoexist.cstate &= ~
1420 rtlpriv->btcoexist.cstate &= ~
1458 rtlpriv->btcoexist.cstate |
[all...]
H A Ddm.c869 rtlpriv->btcoexist.cstate = 0;
/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dbase.c84 struct nouveau_cstate *cstate; local
88 cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
90 cstate = &pstate->base;
102 ret = volt->set_id(volt, cstate->voltage, +1);
109 ret = clk->calc(clk, cstate);
116 ret = volt->set_id(volt, cstate->voltage, -1);
131 nouveau_cstate_del(struct nouveau_cstate *cstate) argument
133 list_del(&cstate->head);
134 kfree(cstate);
143 struct nouveau_cstate *cstate = NULL; local
255 struct nouveau_cstate *cstate; local
296 struct nouveau_cstate *cstate, *temp; local
312 struct nouveau_cstate *cstate; local
[all...]
H A Dnvc0.c263 struct nouveau_cstate *cstate, int clk, int dom)
266 u32 freq = cstate->domain[dom];
283 clk1 = cstate->domain[nv_clk_src_hubk06];
314 nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) argument
319 if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
320 (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
321 (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
322 (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
323 (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
324 (ret = calc_clk(priv, cstate,
262 calc_clk(struct nvc0_clock_priv *priv, struct nouveau_cstate *cstate, int clk, int dom) argument
[all...]
H A Dnva3.c266 calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, argument
269 int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
277 calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) argument
280 u32 kHz = cstate->domain[nv_clk_src_host];
429 nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) argument
435 if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
436 (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
437 (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
438 (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
439 (ret = calc_host(priv, cstate)))
[all...]
H A Dnve0.c281 struct nouveau_cstate *cstate, int clk, int dom)
284 u32 freq = cstate->domain[dom];
301 clk1 = cstate->domain[nv_clk_src_hubk06];
332 nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) argument
337 if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
338 (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
339 (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
340 (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
341 (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
342 (ret = calc_clk(priv, cstate,
280 calc_clk(struct nve0_clock_priv *priv, struct nouveau_cstate *cstate, int clk, int dom) argument
[all...]
H A Dnv40.c151 nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) argument
154 int gclk = cstate->domain[nv_clk_src_core];
155 int sclk = cstate->domain[nv_clk_src_shader];
H A Dnvaa.c202 nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) argument
205 const int shader = cstate->domain[nv_clk_src_shader];
206 const int core = cstate->domain[nv_clk_src_core];
207 const int vdec = cstate->domain[nv_clk_src_vdec];
H A Dnv50.c362 nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) argument
366 const int shader = cstate->domain[nv_clk_src_shader];
367 const int core = cstate->domain[nv_clk_src_core];
368 const int vdec = cstate->domain[nv_clk_src_vdec];
369 const int dom6 = cstate->domain[nv_clk_src_dom6];
H A Dgk20a.c565 gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) argument
569 return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] *
/drivers/gpu/drm/ttm/
H A Dttm_page_alloc.c257 enum ttm_caching_state cstate)
261 if (cstate == tt_cached)
264 if (cstate == tt_wc)
445 enum ttm_caching_state cstate, unsigned cpages)
449 switch (cstate) {
472 int ttm_flags, enum ttm_caching_state cstate,
490 int ttm_flags, enum ttm_caching_state cstate, unsigned count)
517 cstate, cpages);
520 ttm_flags, cstate,
538 cstate, cpage
256 ttm_get_pool(int flags, enum ttm_caching_state cstate) argument
444 ttm_set_pages_caching(struct page **pages, enum ttm_caching_state cstate, unsigned cpages) argument
471 ttm_handle_caching_state_failure(struct list_head *pages, int ttm_flags, enum ttm_caching_state cstate, struct page **failed_pages, unsigned cpages) argument
489 ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, int ttm_flags, enum ttm_caching_state cstate, unsigned count) argument
569 ttm_page_pool_fill_locked(struct ttm_page_pool *pool, int ttm_flags, enum ttm_caching_state cstate, unsigned count, unsigned long *irq_flags) argument
627 ttm_page_pool_get_pages(struct ttm_page_pool *pool, struct list_head *pages, int ttm_flags, enum ttm_caching_state cstate, unsigned count) argument
672 ttm_put_pages(struct page **pages, unsigned npages, int flags, enum ttm_caching_state cstate) argument
720 ttm_get_pages(struct page **pages, unsigned npages, int flags, enum ttm_caching_state cstate) argument
[all...]
H A Dttm_page_alloc_dma.c353 static enum pool_type ttm_to_type(int flags, enum ttm_caching_state cstate) argument
359 if (cstate == tt_cached)
361 else if (cstate == tt_uncached)
/drivers/idle/
H A Dintel_idle.c123 * States are indexed by the cstate number,
572 unsigned int cstate; local
575 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
584 if (!(lapic_timer_reliable_states & (1 << (cstate))))
589 if (!(lapic_timer_reliable_states & (1 << (cstate))))
843 int cstate; local
850 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
853 if (cpuidle_state_table[cstate]
[all...]
/drivers/gpu/drm/nouveau/core/engine/device/
H A Dctrl.c79 struct nouveau_cstate *cstate; local
116 list_for_each_entry(cstate, &pstate->list, head) {
117 lo = min(lo, cstate->domain[domain->name]);
118 hi = max(hi, cstate->domain[domain->name]);
/drivers/gpu/drm/nouveau/core/subdev/therm/
H A Dbase.c121 if (priv->cstate)
122 duty = priv->cstate;
148 if (!dir || (dir < 0 && fan < priv->cstate) ||
149 (dir > 0 && fan > priv->cstate)) {
151 priv->cstate = fan;
H A Dpriv.h79 int cstate; member in struct:nouveau_therm_priv
/drivers/net/slip/
H A Dslhc.c94 register struct cstate *ts;
102 size_t rsize = rslots * sizeof(struct cstate);
110 size_t tsize = tslots * sizeof(struct cstate);
226 register struct cstate *ocs = &(comp->tstate[comp->xmit_oldest]);
227 register struct cstate *lcs = ocs;
228 register struct cstate *cs = lcs->next;
301 * Didn't find it -- re-use oldest cstate. Send an
489 register struct cstate *cs;
632 register struct cstate *cs;
/drivers/block/drbd/
H A Ddrbd_nl.c448 if (connection->cstate >= C_WF_REPORT_PARAMS) {
449 drbd_err(connection, "Expected cstate < C_WF_REPORT_PARAMS\n");
521 if (connection->cstate < C_WF_REPORT_PARAMS && !test_bit(STATE_SENT, &connection->flags)) {
1155 (connection->cstate < C_CONNECTED || connection->agreed_features & FF_TRIM)) {
1241 connection->cstate == C_STANDALONE;
2006 if (old_net_conf && connection->cstate == C_WF_REPORT_PARAMS && connection->agreed_pro_version < 100) {
2212 if (connection->cstate >= C_WF_REPORT_PARAMS && connection->agreed_pro_version >= 100)
2224 if (connection->cstate >= C_WF_REPORT_PARAMS) {
2297 if (connection->cstate > C_STANDALONE) {
3623 if (connection->cstate > C_STANDALON
[all...]
H A Ddrbd_state.c635 /* While establishing a connection only allow cstate to change.
1618 .conn = connection->cstate,
1719 if (connection->cstate != C_WF_REPORT_PARAMS && val.conn == C_WF_REPORT_PARAMS)
1722 connection->cstate = val.conn;
1785 if (err == SS_SUCCESS && connection->cstate == C_WF_REPORT_PARAMS)
1797 enum drbd_conns oc = connection->cstate;
H A Ddrbd_receiver.c510 t = wait_event_timeout(connection->ping_wait, connection->cstate < C_WF_REPORT_PARAMS, t);
990 if (connection->cstate <= C_DISCONNECTING)
1096 if (rv < SS_SUCCESS || connection->cstate != C_WF_REPORT_PARAMS) {
4508 drbd_info(device, "unexpected cstate (%s) in receive_bitmap\n",
4554 drbd_err(device, "ASSERT FAILED cstate = %s, expected: WFSyncUUID|WFBitMapT|Behind\n",
4653 if (connection->cstate == C_STANDALONE)
4690 oc = connection->cstate;
5576 connection->cstate < C_WF_REPORT_PARAMS,
H A Ddrbd_worker.c2119 if (w->cb(w, connection->cstate < C_WF_REPORT_PARAMS) == 0)
2121 if (connection->cstate >= C_WF_REPORT_PARAMS)
H A Ddrbd_main.c1295 if (connection->cstate < C_WF_REPORT_PARAMS)
1440 || connection->cstate < C_WF_REPORT_PARAMS;
1537 } while (len > 0 /* THINK && device->cstate >= C_CONNECTED*/);
2647 connection->cstate = C_STANDALONE;
2846 device->state.conn = first_connection(resource)->cstate;
/drivers/media/platform/marvell-ccic/
H A Dmcam-core.c1996 enum mcam_state cstate = cam->state; local
2000 cam->state = cstate;
/drivers/acpi/
H A Dprocessor_idle.c193 struct acpi_processor_cx *cstate) { }
685 * @cx: cstate data
192 lapic_timer_check_state(int state, struct acpi_processor *pr, struct acpi_processor_cx *cstate) argument

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