Searched refs:mmio_base (Results 1 - 25 of 98) sorted by relevance

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/drivers/input/keyboard/
H A Dimx_keypad.c54 void __iomem *mmio_base; member in struct:imx_keypad
99 reg_val = readw(keypad->mmio_base + KPDR);
101 writew(reg_val, keypad->mmio_base + KPDR);
103 reg_val = readw(keypad->mmio_base + KPCR);
105 writew(reg_val, keypad->mmio_base + KPCR);
109 reg_val = readw(keypad->mmio_base + KPCR);
111 writew(reg_val, keypad->mmio_base + KPCR);
118 reg_val = readw(keypad->mmio_base + KPDR);
120 writew(reg_val, keypad->mmio_base + KPDR);
132 reg_val = readw(keypad->mmio_base
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H A Dpxa930_rotary.c26 void __iomem *mmio_base; member in struct:pxa930_rotary
34 uint32_t sbcr = __raw_readl(r->mmio_base + SBCR);
36 __raw_writel(sbcr | SBCR_ERSB, r->mmio_base + SBCR);
37 __raw_writel(sbcr & ~SBCR_ERSB, r->mmio_base + SBCR);
46 ercr = __raw_readl(r->mmio_base + ERCR) & 0xf;
115 r->mmio_base = ioremap_nocache(res->start, resource_size(res));
116 if (r->mmio_base == NULL) {
171 iounmap(r->mmio_base);
183 iounmap(r->mmio_base);
H A Dw90p910_keypad.c52 void __iomem *mmio_base; member in struct:w90p910_keypad
80 kstatus = __raw_readl(keypad->mmio_base + KPI_STATUS);
99 val = __raw_readl(keypad->mmio_base + KPI_CONF);
107 __raw_writel(val, keypad->mmio_base + KPI_CONF);
170 keypad->mmio_base = ioremap(res->start, resource_size(res));
171 if (keypad->mmio_base == NULL) {
227 iounmap(keypad->mmio_base);
247 iounmap(keypad->mmio_base);
/drivers/pwm/
H A Dpwm-tipwmss.c31 void __iomem *mmio_base; member in struct:pwmss_info
42 val = readw(info->mmio_base + PWMSS_CLKCONFIG);
44 writew(val , info->mmio_base + PWMSS_CLKCONFIG);
47 return readw(info->mmio_base + PWMSS_CLKSTATUS);
71 info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
72 if (IS_ERR(info->mmio_base))
73 return PTR_ERR(info->mmio_base);
102 info->pwmss_clkconfig = readw(info->mmio_base + PWMSS_CLKCONFIG);
112 writew(info->pwmss_clkconfig, info->mmio_base + PWMSS_CLKCONFIG);
H A Dpwm-tiecap.c52 void __iomem *mmio_base; member in struct:ecap_pwm_chip
93 reg_val = readw(pc->mmio_base + ECCTL2);
98 writew(reg_val, pc->mmio_base + ECCTL2);
102 writel(duty_cycles, pc->mmio_base + CAP2);
103 writel(period_cycles, pc->mmio_base + CAP1);
110 writel(duty_cycles, pc->mmio_base + CAP4);
111 writel(period_cycles, pc->mmio_base + CAP3);
115 reg_val = readw(pc->mmio_base + ECCTL2);
118 writew(reg_val, pc->mmio_base + ECCTL2);
132 reg_val = readw(pc->mmio_base
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H A Dpwm-imx.c54 void __iomem *mmio_base; member in struct:imx_chip
87 u32 max = readl(imx->mmio_base + MX1_PWMP);
89 writel(max - p, imx->mmio_base + MX1_PWMS);
99 val = readl(imx->mmio_base + MX1_PWMC);
106 writel(val, imx->mmio_base + MX1_PWMC);
129 sr = readl(imx->mmio_base + MX3_PWMSR);
135 sr = readl(imx->mmio_base + MX3_PWMSR);
140 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
143 cr = readl(imx->mmio_base + MX3_PWMCR);
172 writel(duty_cycles, imx->mmio_base
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H A Dpwm-tiehrpwm.c129 void __iomem *mmio_base; member in struct:ehrpwm_pwm_chip
229 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
295 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
302 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
304 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
307 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
317 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
352 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
355 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
369 ehrpwm_modify(pc->mmio_base, TBCT
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H A Dpwm-spear.c49 * @mmio_base: base address of pwm chip
54 void __iomem *mmio_base; member in struct:spear_pwm_chip
67 return readl_relaxed(chip->mmio_base + (num << 4) + offset);
74 writel_relaxed(val, chip->mmio_base + (num << 4) + offset);
186 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
187 if (IS_ERR(pc->mmio_base))
188 return PTR_ERR(pc->mmio_base);
215 val = readl_relaxed(pc->mmio_base + PWMMCR);
217 writel_relaxed(val, pc->mmio_base + PWMMCR);
H A Dpwm-pxa.c51 void __iomem *mmio_base; member in struct:pxa_pwm_chip
99 writel(prescale, pc->mmio_base + offset + PWMCR);
100 writel(dc, pc->mmio_base + offset + PWMDCR);
101 writel(pv, pc->mmio_base + offset + PWMPCR);
200 pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
201 if (IS_ERR(pwm->mmio_base))
202 return PTR_ERR(pwm->mmio_base);
/drivers/gpu/drm/i915/
H A Dintel_lrc.h28 #define RING_ELSP(ring) ((ring)->mmio_base+0x230)
29 #define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
30 #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
31 #define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
32 #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
H A Dintel_ringbuffer.h32 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
33 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
35 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
36 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
38 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
39 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
41 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
42 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
44 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
45 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), va
137 u32 mmio_base; member in struct:intel_engine_cs
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/drivers/watchdog/
H A Dep93xx_wdt.c50 static void __iomem *mmio_base; variable
63 writel(0x5555, mmio_base + EP93XX_WATCHDOG);
73 writel(0xaaaa, mmio_base + EP93XX_WATCHDOG);
82 writel(0xaa55, mmio_base + EP93XX_WATCHDOG);
121 mmio_base = devm_ioremap_resource(&pdev->dev, res);
122 if (IS_ERR(mmio_base))
123 return PTR_ERR(mmio_base);
132 val = readl(mmio_base + EP93XX_WATCHDOG);
/drivers/input/mouse/
H A Dpxa930_trkball.c47 void __iomem *mmio_base; member in struct:pxa930_trkball
61 tbcntr = __raw_readl(trkball->mmio_base + TBCNTR);
63 if (tbcntr == __raw_readl(trkball->mmio_base + TBCNTR)) {
72 __raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC);
73 __raw_writel(0, trkball->mmio_base + TBSBC);
83 __raw_writel(v, trkball->mmio_base + TBCR);
86 if (__raw_readl(trkball->mmio_base + TBCR) == v)
104 tbcr = __raw_readl(trkball->mmio_base + TBCR);
110 tbcr = __raw_readl(trkball->mmio_base + TBCR);
114 __raw_writel(TBSBC_TBSBC, trkball->mmio_base
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/drivers/net/wireless/b43/
H A Dpio.h71 u16 mmio_base; member in struct:b43_pio_txqueue
100 u16 mmio_base; member in struct:b43_pio_rxqueue
110 return b43_read16(q->dev, q->mmio_base + offset);
115 return b43_read32(q->dev, q->mmio_base + offset);
121 b43_write16(q->dev, q->mmio_base + offset, value);
127 b43_write32(q->dev, q->mmio_base + offset, value);
133 return b43_read16(q->dev, q->mmio_base + offset);
138 return b43_read32(q->dev, q->mmio_base + offset);
144 b43_write16(q->dev, q->mmio_base + offset, value);
150 b43_write32(q->dev, q->mmio_base
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/drivers/ata/
H A Dsata_sil.c270 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local
271 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
296 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local
297 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2;
363 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local
364 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
524 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; local
532 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
553 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local
557 writel(0, mmio_base
581 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local
665 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; local
739 void __iomem *mmio_base; local
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H A Dpata_pdc2027x.c478 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; local
484 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
485 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
488 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
489 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
519 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; local
538 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
578 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
579 ioread16(mmio_base + PDC_PLL_CTL); /* flush */
589 pll_ctl = ioread16(mmio_base
605 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; local
713 void __iomem *mmio_base; local
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H A Dsata_qstor.c208 u8 __iomem *mmio_base = qs_mmio_base(ap->host); local
210 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
216 u8 __iomem *mmio_base = qs_mmio_base(ap->host); local
219 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
375 u8 __iomem *mmio_base = qs_mmio_base(host); local
378 u32 sff0 = readl(mmio_base + QS_HST_SFF);
379 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
485 void __iomem *mmio_base = qs_mmio_base(ap->host); local
486 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
508 void __iomem *mmio_base local
516 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR]; local
554 qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) argument
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/drivers/rtc/
H A Drtc-ep93xx.c38 void __iomem *mmio_base; member in struct:ep93xx_rtc
48 comp = __raw_readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP);
66 time = __raw_readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA);
76 __raw_writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD);
141 ep93xx_rtc->mmio_base = devm_ioremap_resource(&pdev->dev, res);
142 if (IS_ERR(ep93xx_rtc->mmio_base))
143 return PTR_ERR(ep93xx_rtc->mmio_base);
/drivers/net/wireless/b43legacy/
H A Dpio.h52 u16 mmio_base; member in struct:b43legacy_pioqueue
86 return b43legacy_read16(queue->dev, queue->mmio_base + offset);
93 b43legacy_write16(queue->dev, queue->mmio_base + offset, value);
/drivers/mtd/nand/
H A Dcs553x_nand.c144 void __iomem *mmio_base = this->IO_ADDR_R; local
147 writeb(ctl, mmio_base + MM_NAND_CTL);
156 void __iomem *mmio_base = this->IO_ADDR_R; local
157 unsigned char foo = readb(mmio_base + MM_NAND_STS);
165 void __iomem *mmio_base = this->IO_ADDR_R; local
167 writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
174 void __iomem *mmio_base = this->IO_ADDR_R; local
176 ecc = readl(mmio_base + MM_NAND_STS);
329 void __iomem *mmio_base; local
335 mmio_base
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/drivers/usb/host/
H A Dohci-pxa27x.c123 void __iomem *mmio_base; member in struct:pxa27x_ohci
142 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
143 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
167 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
168 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
223 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
224 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
256 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
257 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
262 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base
[all...]
/drivers/scsi/ufs/
H A Dufshcd-pci.c123 void __iomem *mmio_base; local
140 mmio_base = pcim_iomap_table(pdev)[0];
150 err = ufshcd_init(hba, mmio_base, pdev->irq);
/drivers/acpi/
H A Dacpi_lpss.c78 void __iomem *mmio_base; member in struct:lpss_private_data
96 val = readl(pdata->mmio_base + offset);
97 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
99 val = readl(pdata->mmio_base + LPSS_UART_CPR);
102 val = readl(pdata->mmio_base + offset);
104 writel(val, pdata->mmio_base + offset);
114 val = readl(pdata->mmio_base + offset);
116 writel(val, pdata->mmio_base + offset);
118 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
253 if (!pdata->mmio_base
[all...]
/drivers/thermal/st/
H A Dst_thermal_memmap.c135 sensor->mmio_base = devm_ioremap_resource(dev, res);
136 if (IS_ERR(sensor->mmio_base)) {
138 return PTR_ERR(sensor->mmio_base);
141 sensor->regmap = devm_regmap_init_mmio(dev, sensor->mmio_base,
/drivers/gpio/
H A Dgpio-ep93xx.c30 void __iomem *mmio_base; member in struct:ep93xx_gpio
322 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
324 void __iomem *data = mmio_base + bank->data;
325 void __iomem *dir = mmio_base + bank->dir;
355 ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
356 if (IS_ERR(ep93xx_gpio->mmio_base))
357 return PTR_ERR(ep93xx_gpio->mmio_base);
364 ep93xx_gpio->mmio_base, bank))
321 ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev, void __iomem *mmio_base, struct ep93xx_gpio_bank *bank) argument

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