/drivers/clk/berlin/ |
H A D | berlin2-div.c | 26 #include "berlin2-div.h" 46 * (D) constant div-by-3 clock divider 48 * (F) constant div-by-3 clock mux controlled by <D3Switch> 56 * Also, clock gate and pll mux is not available on every div cell, so 77 struct berlin2_div *div = to_berlin2_div(hw); local 78 struct berlin2_div_map *map = &div->map; 81 if (div->lock) 82 spin_lock(div->lock); 84 reg = readl_relaxed(div->base + map->gate_offs); 87 if (div 95 struct berlin2_div *div = to_berlin2_div(hw); local 114 struct berlin2_div *div = to_berlin2_div(hw); local 131 struct berlin2_div *div = to_berlin2_div(hw); local 162 struct berlin2_div *div = to_berlin2_div(hw); local 189 struct berlin2_div *div = to_berlin2_div(hw); local 246 struct berlin2_div *div; local [all...] |
H A D | Makefile | 1 obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
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/drivers/clk/mxs/ |
H A D | clk-div.c | 45 struct clk_div *div = to_clk_div(hw); local 47 return div->ops->recalc_rate(&div->divider.hw, parent_rate); 53 struct clk_div *div = to_clk_div(hw); local 55 return div->ops->round_rate(&div->divider.hw, rate, prate); 61 struct clk_div *div = to_clk_div(hw); local 64 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); 66 ret = mxs_clk_wait(div 80 struct clk_div *div; local [all...] |
H A D | clk-frac.c | 44 u32 div; local 46 div = readl_relaxed(frac->reg) >> frac->shift; 47 div &= (1 << frac->width) - 1; 49 return (parent_rate >> frac->width) * div; 57 u32 div; local 66 div = tmp; 68 if (!div) 71 return (parent_rate >> frac->width) * div; 79 u32 div, val; local 88 div [all...] |
/drivers/clk/ |
H A D | clk-divider.c | 40 for (clkt = table; clkt->div; clkt++) 41 if (clkt->div > maxdiv) 42 maxdiv = clkt->div; 51 for (clkt = table; clkt->div; clkt++) 52 if (clkt->div < mindiv) 53 mindiv = clkt->div; 73 for (clkt = table; clkt->div; clkt++) 75 return clkt->div; 91 unsigned int div) 95 for (clkt = table; clkt->div; clk 90 _get_table_val(const struct clk_div_table *table, unsigned int div) argument 101 _get_val(struct clk_divider *divider, unsigned int div) argument 116 unsigned int div, val; local 138 _is_valid_table_div(const struct clk_div_table *table, unsigned int div) argument 149 _is_valid_div(struct clk_divider *divider, unsigned int div) argument 158 _round_up_table(const struct clk_div_table *table, int div) argument 176 _round_down_table(const struct clk_div_table *table, int div) argument 197 int div = DIV_ROUND_UP(parent_rate, rate); local 210 int up, down, div; local 243 _next_div(struct clk_divider *divider, int div) argument 323 int div; local 333 unsigned int div, value; local 378 struct clk_divider *div; local [all...] |
H A D | clk-fixed-factor.c | 22 * rate - rate is fixed. clk->rate = parent->rate / div * mult 35 do_div(rate, fix->div); 47 best_parent = (rate / fix->mult) * fix->div; 52 return (*prate / fix->div) * fix->mult; 70 unsigned int mult, unsigned int div) 84 fix->div = div; 111 u32 div, mult; local 113 if (of_property_read_u32(node, "clock-div", &div)) { 68 clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) argument [all...] |
/drivers/mmc/host/ |
H A D | sdhci-cns3xxx.c | 29 int div = 1; local 40 while (host->max_clk / div > clock) { 45 if (div < 4) 46 div += 1; 47 else if (div < 256) 48 div *= 2; 54 clock, host->max_clk / div); 57 if (div != 3) 58 div >>= 1; 60 clk = div << SDHCI_DIVIDER_SHIF [all...] |
/drivers/clk/ti/ |
H A D | divider.c | 37 for (clkt = table; clkt->div; clkt++) 38 if (clkt->div > maxdiv) 39 maxdiv = clkt->div; 59 for (clkt = table; clkt->div; clkt++) 61 return clkt->div; 77 unsigned int div) 81 for (clkt = table; clkt->div; clkt++) 82 if (clkt->div == div) 87 static unsigned int _get_val(struct clk_divider *divider, u8 div) argument 76 _get_table_val(const struct clk_div_table *table, unsigned int div) argument 102 unsigned int div, val; local 124 _is_valid_table_div(const struct clk_div_table *table, unsigned int div) argument 135 _is_valid_div(struct clk_divider *divider, unsigned int div) argument 205 int div; local 215 unsigned int div, value; local 261 struct clk_divider *div; local 360 u32 div; local 473 struct clk_divider *div; local [all...] |
H A D | fixed-factor.c | 39 u32 div, mult; local 42 if (of_property_read_u32(node, "ti,clock-div", &div)) { 43 pr_err("%s must have a clock-div property\n", node->name); 58 mult, div);
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/drivers/clk/sunxi/ |
H A D | clk-sun8i-mbus.c | 32 u8 div; local 41 div = DIV_ROUND_UP(parent_rate, *freq); 43 if (div > 8) 44 div = 8; 46 *freq = parent_rate / div; 52 *m = div - 1;
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H A D | clk-sunxi.c | 41 u8 div; local 44 div = *freq / 6000000; 45 *freq = 6000000 * div; 61 if (div < 10) 65 else if (div < 20 || (div < 32 && (div & 1))) 70 else if (div < 40 || (div < 64 && (div 177 u8 div; local 225 u8 div; local 257 u8 div; local 333 u8 div, calcm, calcp; local 902 } div[SUNXI_DIVS_MAX_QTY]; member in struct:divs_data [all...] |
H A D | clk-sun6i-apb0.c | 24 { .val = 0, .div = 2, }, 25 { .val = 1, .div = 2, }, 26 { .val = 2, .div = 4, }, 27 { .val = 3, .div = 8, },
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/drivers/media/i2c/ |
H A D | aptina-pll.c | 38 unsigned int div; local 55 div = gcd(pll->pix_clock, pll->ext_clock); 56 pll->m = pll->pix_clock / div; 57 div = pll->ext_clock / div; 72 mf_min = max(mf_min, limits->n_min * limits->p1_min / div); 76 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); 91 * 3. div * mf is a multiple of p1, in order to compute 92 * n = div * mf / p1 108 * mf_inc = p1 / gcd(div, p [all...] |
/drivers/clk/tegra/ |
H A D | clk-divider.c | 72 int div, mul; local 76 div = reg & div_mask(divider); 79 div += mul; 82 rate += div - 1; 83 do_div(rate, div); 92 int div, mul; local 98 div = get_div(divider, rate, output_rate); 99 if (div < 0) 104 return DIV_ROUND_UP(output_rate * mul, div + mul); 111 int div; local [all...] |
/drivers/clk/shmobile/ |
H A D | clk-div6.c | 29 * @div: divisor value (1-64) 34 unsigned int div; member in struct:div6_clock 43 clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); 70 unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; local 72 return parent_rate / div; 78 unsigned int div; local 80 div = DIV_ROUND_CLOSEST(parent_rate, rate); 81 return clamp_t(unsigned int, div, 1, 64); 87 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); local 89 return *parent_rate / div; 96 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); local [all...] |
H A D | clk-r8a7779.c | 100 unsigned int div = 1; local 106 div = config->z_div; 109 div = config->zs_and_s_div; 111 div = config->s1_div; 113 div = config->p_div; 115 div = config->b_and_out_div; 120 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
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/drivers/gpu/drm/armada/ |
H A D | armada_510.c | 64 uint32_t rate, ref, div; local 68 div = DIV_ROUND_UP(ref, rate); 69 if (div < 1) 70 div = 1; 73 *sclk = div | SCLK_510_EXTCLK1;
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/drivers/clk/bcm/ |
H A D | clk-kona.c | 70 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) argument 72 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); 80 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) argument 88 combined <<= div->u.s.frac_width; 95 scaled_div_min(struct bcm_clk_div *div) argument 97 if (divider_is_fixed(div)) 98 return (u64)div->u.fixed; 100 return scaled_div_value(div, 0); 104 u64 scaled_div_max(struct bcm_clk_div *div) argument 108 if (divider_is_fixed(div)) 121 divider(struct bcm_clk_div *div, u64 scaled_div) argument 131 scale_rate(struct bcm_clk_div *div, u32 rate) argument 576 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div) argument 603 __div_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate, struct bcm_clk_div *div, struct bcm_clk_trig *trig) argument 659 div_init(struct ccu_data *ccu, struct bcm_clk_gate *gate, struct bcm_clk_div *div, struct bcm_clk_trig *trig) argument 667 divider_write(struct ccu_data *ccu, struct bcm_clk_gate *gate, struct bcm_clk_div *div, struct bcm_clk_trig *trig, u64 scaled_div) argument 705 clk_recalc_rate(struct ccu_data *ccu, struct bcm_clk_div *div, struct bcm_clk_div *pre_div, unsigned long parent_rate) argument 760 round_rate(struct ccu_data *ccu, struct bcm_clk_div *div, struct bcm_clk_div *pre_div, unsigned long rate, unsigned long parent_rate, u64 *scaled_div) argument 1024 struct bcm_clk_div *div = &bcm_clk->u.peri->div; local 1138 struct bcm_clk_div *div = &data->div; local [all...] |
H A D | clk-kona-setup.c | 57 struct bcm_clk_div *div; local 66 div = &peri->div; 67 if (!divider_exists(div)) 71 if (!divider_is_fixed(div)) 74 div = &peri->pre_div; 76 return divider_exists(div) && !divider_is_fixed(div); 85 struct bcm_clk_div *div; local 131 div 337 div_valid(struct bcm_clk_div *div, const char *field_name, const char *clock_name) argument 373 struct bcm_clk_div *div; local 409 struct bcm_clk_div *div; local [all...] |
/drivers/clk/rockchip/ |
H A D | clk.c | 52 struct clk_divider *div = NULL; local 83 div = kzalloc(sizeof(*div), GFP_KERNEL); 84 if (!div) 87 div->flags = div_flags; 88 div->reg = base + muxdiv_offset; 89 div->shift = div_shift; 90 div->width = div_width; 91 div->lock = lock; 92 div 113 struct clk_fractional_divider *div = NULL; local [all...] |
/drivers/clk/spear/ |
H A D | spear1340_clock.c | 192 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */ 193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */ 194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */ 195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */ 196 {.div = 0x03031}, /* for vco1div2 = 250 MHz */ 197 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */ 210 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div 244 {.div = 0x08000}, 245 {.div = 0x06a38}, 246 {.div [all...] |
/drivers/clk/mvebu/ |
H A D | orion.c | 60 int *mult, int *div) 66 *div = 2; 69 *div = 3; 72 *div = 1; 117 int *mult, int *div) 123 *div = 2; 126 *div = 3; 129 *div = 1; 183 int *mult, int *div) 189 *div 59 mv88f5182_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) argument 116 mv88f5281_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) argument 182 mv88f6183_get_clk_ratio(void __iomem *sar, int id, int *mult, int *div) argument [all...] |
/drivers/media/dvb-frontends/ |
H A D | tdhd1.h | 49 u32 div; local 51 div = (p->frequency + 36166666) / 166666; 53 data[0] = (div >> 8) & 0x7f; 54 data[1] = div & 0xff;
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/drivers/media/tuners/ |
H A D | tea5767.c | 60 /* if on, div=4*(Frf+Fif)/Fref otherwise, div=4*(Frf-Fif)/Freq) */ 136 unsigned int div, frq; local 148 div = ((buffer[0] & 0x3f) << 8) | buffer[1]; 152 frq = (div * 50000 - 700000 - 225000) / 4; /* Freq in KHz */ 155 frq = (div * 50000 + 700000 + 225000) / 4; /* Freq in KHz */ 158 frq = (div * 32768 + 700000 + 225000) / 4; /* Freq in KHz */ 162 frq = (div * 32768 - 700000 - 225000) / 4; /* Freq in KHz */ 165 buffer[0] = (div >> 8) & 0x3f; 166 buffer[1] = div 194 unsigned div; local 353 unsigned div, rc; local [all...] |
/drivers/gpu/drm/nouveau/ |
H A D | nouveau_backlight.c | 102 u32 div = 1025; local 107 return ((val * 100) + (div / 2)) / div; 117 u32 div = 1025; local 118 u32 val = (bd->props.brightness * div) / 100; 138 u32 div, val; local 140 div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); 143 if (div && div >= val) 144 return ((val * 100) + (div / 156 u32 div, val; local [all...] |