Searched refs:mfc_write (Results 1 - 6 of 6) sorted by relevance

/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_cmd_v6.c27 mfc_write(dev, 0x0, S5P_FIMV_RISC2HOST_CMD_V6);
30 mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD_V6);
31 mfc_write(dev, 0x1, S5P_FIMV_HOST2RISC_INT_V6);
42 mfc_write(dev, dev->ctx_buf.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
43 mfc_write(dev, buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
118 mfc_write(dev, codec_type, S5P_FIMV_CODEC_TYPE_V6);
119 mfc_write(dev, ctx->ctx.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
120 mfc_write(dev, ctx->ctx.size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
121 mfc_write(dev, 0, S5P_FIMV_D_CRC_CTRL_V6); /* no crc */
136 mfc_write(de
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H A Ds5p_mfc_ctrl.c144 mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6);
146 mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6);
149 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
150 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
151 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
154 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
157 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
158 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
159 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
163 mfc_write(de
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H A Ds5p_mfc_opr_v5.c353 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR);
354 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE);
361 mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR);
371 mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR);
372 mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE);
373 mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE);
394 mfc_write(dev, ctx->total_dpb_count | dpb,
399 mfc_write(dev, OFFSETA(buf_addr1),
403 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR);
408 mfc_write(de
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H A Ds5p_mfc_cmd_v5.c35 mfc_write(dev, args->arg[0], S5P_FIMV_HOST2RISC_ARG1);
36 mfc_write(dev, args->arg[1], S5P_FIMV_HOST2RISC_ARG2);
37 mfc_write(dev, args->arg[2], S5P_FIMV_HOST2RISC_ARG3);
38 mfc_write(dev, args->arg[3], S5P_FIMV_HOST2RISC_ARG4);
40 mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD);
H A Ds5p_mfc_common.h106 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \ macro
H A Ds5p_mfc.c182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);

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