Searched refs:val (Results 1 - 25 of 1331) sorted by relevance

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/arch/alpha/lib/
H A Dfpreg.c8 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val));
10 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val));
16 unsigned long val; local
19 case 0: STT( 0, val); break;
20 case 1: STT( 1, val); break;
21 case 2: STT( 2, val); break;
22 case 3: STT( 3, val); break;
23 case 4: STT( 4, val); brea
63 alpha_write_fp_reg(unsigned long reg, unsigned long val) argument
110 unsigned long val; local
157 alpha_write_fp_reg_s(unsigned long reg, unsigned long val) argument
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/arch/x86/lib/
H A Dmisc.c2 * Count the digits of @val including a possible sign.
6 int num_digits(int val) argument
11 if (val < 0) {
13 val = -val;
16 while (val >= m) {
/arch/c6x/include/uapi/asm/
H A Dswab.h12 static inline __attribute_const__ __u16 __c6x_swab16(__u16 val) argument
14 asm("swap4 .l1 %0,%0\n" : "+a"(val));
15 return val;
18 static inline __attribute_const__ __u32 __c6x_swab32(__u32 val) argument
22 : "+a"(val));
23 return val;
26 static inline __attribute_const__ __u64 __c6x_swab64(__u64 val) argument
32 : "+a"(val));
33 return val;
36 static inline __attribute_const__ __u32 __c6x_swahw32(__u32 val) argument
42 __c6x_swahb32(__u32 val) argument
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/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF539.h14 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
16 #define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
18 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
20 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
22 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
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H A DcdefBF538.h10 #define bfin_writePTR(addr, val) bfin_write32(addr, val)
14 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
17 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
19 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
21 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
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/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF516.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
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H A DcdefBF518.h16 #define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
18 #define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
20 #define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
22 #define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
24 #define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
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H A DcdefBF514.h16 #define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
18 #define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
20 #define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
22 #define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
24 #define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
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/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF527.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
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H A DcdefBF522.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
20 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
25 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
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/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF537.h16 #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
18 #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
20 #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
22 #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
24 #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
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H A DcdefBF534.h13 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
16 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
18 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
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/arch/blackfin/mach-bf548/include/mach/
H A DcdefBF544.h18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
20 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
22 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
24 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
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H A DcdefBF549.h19 #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
21 #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
23 #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
25 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
27 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
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H A DcdefBF542.h18 #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
20 #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
22 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
24 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
26 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
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H A DcdefBF54x_base.h18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
21 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
23 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
28 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
33 #define bfin_write_SWRST(val) bfin_write16(SWRST, val)
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H A DcdefBF548.h19 #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
21 #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
23 #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
25 #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
27 #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
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H A DcdefBF547.h18 #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
20 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
22 #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
24 #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
26 #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
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/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h13 #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
15 #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
18 #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
23 #define bfin_write_SWRST(val) bfin_write16(SWRST,val)
25 #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
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/arch/blackfin/mach-bf609/include/mach/
H A DcdefBF60x_base.h17 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
23 #define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
25 #define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
27 #define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
30 #define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
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/arch/x86/include/asm/
H A Dspecial_insns.h23 unsigned long val; local
24 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
25 return val;
28 static inline void native_write_cr0(unsigned long val) argument
30 asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
35 unsigned long val; local
36 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
37 return val;
40 static inline void native_write_cr2(unsigned long val) argument
42 asm volatile("mov %0,%%cr2": : "r" (val), "
47 unsigned long val; local
52 native_write_cr3(unsigned long val) argument
59 unsigned long val; local
66 unsigned long val; local
80 native_write_cr4(unsigned long val) argument
93 native_write_cr8(unsigned long val) argument
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H A Dmisc.h4 int num_digits(int val);
/arch/blackfin/include/asm/
H A Dcdef_LPBlackfin.h18 #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
20 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
22 #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
24 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
29 #define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
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/arch/m68k/include/uapi/asm/
H A Dswab.h10 static inline __attribute_const__ __u32 __arch_swab32(__u32 val) argument
12 __asm__("byterev %0" : "=d" (val) : "0" (val));
13 return val;
19 static inline __attribute_const__ __u32 __arch_swab32(__u32 val) argument
21 __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val));
22 return val;
/arch/arm/include/asm/
H A Dcp15.h56 unsigned long val; local
57 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
58 return val;
61 static inline void set_cr(unsigned long val) argument
64 : : "r" (val) : "cc");
70 unsigned int val; local
71 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
72 return val;
75 static inline void set_auxcr(unsigned int val) argument
78 : : "r" (val));
88 unsigned int val; local
94 set_copro_access(unsigned int val) argument
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