1/* 2 * TI DaVinci DM365 EVM board support 3 * 4 * Copyright (C) 2009 Texas Instruments Incorporated 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15#include <linux/kernel.h> 16#include <linux/init.h> 17#include <linux/err.h> 18#include <linux/i2c.h> 19#include <linux/io.h> 20#include <linux/clk.h> 21#include <linux/platform_data/at24.h> 22#include <linux/leds.h> 23#include <linux/mtd/mtd.h> 24#include <linux/mtd/partitions.h> 25#include <linux/slab.h> 26#include <linux/mtd/nand.h> 27#include <linux/input.h> 28#include <linux/spi/spi.h> 29#include <linux/spi/eeprom.h> 30#include <linux/v4l2-dv-timings.h> 31 32#include <asm/mach-types.h> 33#include <asm/mach/arch.h> 34 35#include <mach/mux.h> 36#include <mach/common.h> 37#include <linux/platform_data/i2c-davinci.h> 38#include <mach/serial.h> 39#include <linux/platform_data/mmc-davinci.h> 40#include <linux/platform_data/mtd-davinci.h> 41#include <linux/platform_data/keyscan-davinci.h> 42 43#include <media/ths7303.h> 44#include <media/tvp514x.h> 45 46#include "davinci.h" 47 48static inline int have_imager(void) 49{ 50 /* REVISIT when it's supported, trigger via Kconfig */ 51 return 0; 52} 53 54static inline int have_tvp7002(void) 55{ 56 /* REVISIT when it's supported, trigger via Kconfig */ 57 return 0; 58} 59 60#define DM365_EVM_PHY_ID "davinci_mdio-0:01" 61/* 62 * A MAX-II CPLD is used for various board control functions. 63 */ 64#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) 65 66#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ 67#define CPLD_TEST CPLD_OFFSET(0,1) 68#define CPLD_LEDS CPLD_OFFSET(0,2) 69#define CPLD_MUX CPLD_OFFSET(0,3) 70#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ 71#define CPLD_POWER CPLD_OFFSET(1,1) 72#define CPLD_VIDEO CPLD_OFFSET(1,2) 73#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ 74 75#define CPLD_DILC_OUT CPLD_OFFSET(2,0) 76#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ 77 78#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) 79#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) 80#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) 81#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) 82#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) 83#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) 84#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) 85#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) 86#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) 87 88#define CPLD_RESETS CPLD_OFFSET(4,3) 89 90#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) 91#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) 92#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) 93#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) 94#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) 95#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) 96 97static void __iomem *cpld; 98 99 100/* NOTE: this is geared for the standard config, with a socketed 101 * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you 102 * swap chips with a different block size, partitioning will 103 * need to be changed. This NAND chip MT29F16G08FAA is the default 104 * NAND shipped with the Spectrum Digital DM365 EVM 105 */ 106#define NAND_BLOCK_SIZE SZ_128K 107 108static struct mtd_partition davinci_nand_partitions[] = { 109 { 110 /* UBL (a few copies) plus U-Boot */ 111 .name = "bootloader", 112 .offset = 0, 113 .size = 30 * NAND_BLOCK_SIZE, 114 .mask_flags = MTD_WRITEABLE, /* force read-only */ 115 }, { 116 /* U-Boot environment */ 117 .name = "params", 118 .offset = MTDPART_OFS_APPEND, 119 .size = 2 * NAND_BLOCK_SIZE, 120 .mask_flags = 0, 121 }, { 122 .name = "kernel", 123 .offset = MTDPART_OFS_APPEND, 124 .size = SZ_4M, 125 .mask_flags = 0, 126 }, { 127 .name = "filesystem1", 128 .offset = MTDPART_OFS_APPEND, 129 .size = SZ_512M, 130 .mask_flags = 0, 131 }, { 132 .name = "filesystem2", 133 .offset = MTDPART_OFS_APPEND, 134 .size = MTDPART_SIZ_FULL, 135 .mask_flags = 0, 136 } 137 /* two blocks with bad block table (and mirror) at the end */ 138}; 139 140static struct davinci_nand_pdata davinci_nand_data = { 141 .mask_chipsel = BIT(14), 142 .parts = davinci_nand_partitions, 143 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 144 .ecc_mode = NAND_ECC_HW, 145 .bbt_options = NAND_BBT_USE_FLASH, 146 .ecc_bits = 4, 147}; 148 149static struct resource davinci_nand_resources[] = { 150 { 151 .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, 152 .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, 153 .flags = IORESOURCE_MEM, 154 }, { 155 .start = DM365_ASYNC_EMIF_CONTROL_BASE, 156 .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, 157 .flags = IORESOURCE_MEM, 158 }, 159}; 160 161static struct platform_device davinci_nand_device = { 162 .name = "davinci_nand", 163 .id = 0, 164 .num_resources = ARRAY_SIZE(davinci_nand_resources), 165 .resource = davinci_nand_resources, 166 .dev = { 167 .platform_data = &davinci_nand_data, 168 }, 169}; 170 171static struct at24_platform_data eeprom_info = { 172 .byte_len = (256*1024) / 8, 173 .page_size = 64, 174 .flags = AT24_FLAG_ADDR16, 175 .setup = davinci_get_mac_addr, 176 .context = (void *)0x7f00, 177}; 178 179static struct snd_platform_data dm365_evm_snd_data __maybe_unused = { 180 .asp_chan_q = EVENTQ_3, 181}; 182 183static struct i2c_board_info i2c_info[] = { 184 { 185 I2C_BOARD_INFO("24c256", 0x50), 186 .platform_data = &eeprom_info, 187 }, 188 { 189 I2C_BOARD_INFO("tlv320aic3x", 0x18), 190 }, 191}; 192 193static struct davinci_i2c_platform_data i2c_pdata = { 194 .bus_freq = 400 /* kHz */, 195 .bus_delay = 0 /* usec */, 196}; 197 198static int dm365evm_keyscan_enable(struct device *dev) 199{ 200 return davinci_cfg_reg(DM365_KEYSCAN); 201} 202 203static unsigned short dm365evm_keymap[] = { 204 KEY_KP2, 205 KEY_LEFT, 206 KEY_EXIT, 207 KEY_DOWN, 208 KEY_ENTER, 209 KEY_UP, 210 KEY_KP1, 211 KEY_RIGHT, 212 KEY_MENU, 213 KEY_RECORD, 214 KEY_REWIND, 215 KEY_KPMINUS, 216 KEY_STOP, 217 KEY_FASTFORWARD, 218 KEY_KPPLUS, 219 KEY_PLAYPAUSE, 220 0 221}; 222 223static struct davinci_ks_platform_data dm365evm_ks_data = { 224 .device_enable = dm365evm_keyscan_enable, 225 .keymap = dm365evm_keymap, 226 .keymapsize = ARRAY_SIZE(dm365evm_keymap), 227 .rep = 1, 228 /* Scan period = strobe + interval */ 229 .strobe = 0x5, 230 .interval = 0x2, 231 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4, 232}; 233 234static int cpld_mmc_get_cd(int module) 235{ 236 if (!cpld) 237 return -ENXIO; 238 239 /* low == card present */ 240 return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); 241} 242 243static int cpld_mmc_get_ro(int module) 244{ 245 if (!cpld) 246 return -ENXIO; 247 248 /* high == card's write protect switch active */ 249 return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); 250} 251 252static struct davinci_mmc_config dm365evm_mmc_config = { 253 .get_cd = cpld_mmc_get_cd, 254 .get_ro = cpld_mmc_get_ro, 255 .wires = 4, 256 .max_freq = 50000000, 257 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, 258}; 259 260static void dm365evm_emac_configure(void) 261{ 262 /* 263 * EMAC pins are multiplexed with GPIO and UART 264 * Further details are available at the DM365 ARM 265 * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 266 */ 267 davinci_cfg_reg(DM365_EMAC_TX_EN); 268 davinci_cfg_reg(DM365_EMAC_TX_CLK); 269 davinci_cfg_reg(DM365_EMAC_COL); 270 davinci_cfg_reg(DM365_EMAC_TXD3); 271 davinci_cfg_reg(DM365_EMAC_TXD2); 272 davinci_cfg_reg(DM365_EMAC_TXD1); 273 davinci_cfg_reg(DM365_EMAC_TXD0); 274 davinci_cfg_reg(DM365_EMAC_RXD3); 275 davinci_cfg_reg(DM365_EMAC_RXD2); 276 davinci_cfg_reg(DM365_EMAC_RXD1); 277 davinci_cfg_reg(DM365_EMAC_RXD0); 278 davinci_cfg_reg(DM365_EMAC_RX_CLK); 279 davinci_cfg_reg(DM365_EMAC_RX_DV); 280 davinci_cfg_reg(DM365_EMAC_RX_ER); 281 davinci_cfg_reg(DM365_EMAC_CRS); 282 davinci_cfg_reg(DM365_EMAC_MDIO); 283 davinci_cfg_reg(DM365_EMAC_MDCLK); 284 285 /* 286 * EMAC interrupts are multiplexed with GPIO interrupts 287 * Details are available at the DM365 ARM 288 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 289 */ 290 davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); 291 davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); 292 davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); 293 davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); 294} 295 296static void dm365evm_mmc_configure(void) 297{ 298 /* 299 * MMC/SD pins are multiplexed with GPIO and EMIF 300 * Further details are available at the DM365 ARM 301 * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 302 */ 303 davinci_cfg_reg(DM365_SD1_CLK); 304 davinci_cfg_reg(DM365_SD1_CMD); 305 davinci_cfg_reg(DM365_SD1_DATA3); 306 davinci_cfg_reg(DM365_SD1_DATA2); 307 davinci_cfg_reg(DM365_SD1_DATA1); 308 davinci_cfg_reg(DM365_SD1_DATA0); 309} 310 311static struct tvp514x_platform_data tvp5146_pdata = { 312 .clk_polarity = 0, 313 .hs_polarity = 1, 314 .vs_polarity = 1 315}; 316 317#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) 318/* Inputs available at the TVP5146 */ 319static struct v4l2_input tvp5146_inputs[] = { 320 { 321 .index = 0, 322 .name = "Composite", 323 .type = V4L2_INPUT_TYPE_CAMERA, 324 .std = TVP514X_STD_ALL, 325 }, 326 { 327 .index = 1, 328 .name = "S-Video", 329 .type = V4L2_INPUT_TYPE_CAMERA, 330 .std = TVP514X_STD_ALL, 331 }, 332}; 333 334/* 335 * this is the route info for connecting each input to decoder 336 * ouput that goes to vpfe. There is a one to one correspondence 337 * with tvp5146_inputs 338 */ 339static struct vpfe_route tvp5146_routes[] = { 340 { 341 .input = INPUT_CVBS_VI2B, 342 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, 343 }, 344{ 345 .input = INPUT_SVIDEO_VI2C_VI1C, 346 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, 347 }, 348}; 349 350static struct vpfe_subdev_info vpfe_sub_devs[] = { 351 { 352 .name = "tvp5146", 353 .grp_id = 0, 354 .num_inputs = ARRAY_SIZE(tvp5146_inputs), 355 .inputs = tvp5146_inputs, 356 .routes = tvp5146_routes, 357 .can_route = 1, 358 .ccdc_if_params = { 359 .if_type = VPFE_BT656, 360 .hdpol = VPFE_PINPOL_POSITIVE, 361 .vdpol = VPFE_PINPOL_POSITIVE, 362 }, 363 .board_info = { 364 I2C_BOARD_INFO("tvp5146", 0x5d), 365 .platform_data = &tvp5146_pdata, 366 }, 367 }, 368}; 369 370static struct vpfe_config vpfe_cfg = { 371 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), 372 .sub_devs = vpfe_sub_devs, 373 .i2c_adapter_id = 1, 374 .card_name = "DM365 EVM", 375 .ccdc = "ISIF", 376}; 377 378/* venc standards timings */ 379static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = { 380 { 381 .name = "ntsc", 382 .timings_type = VPBE_ENC_STD, 383 .std_id = V4L2_STD_NTSC, 384 .interlaced = 1, 385 .xres = 720, 386 .yres = 480, 387 .aspect = {11, 10}, 388 .fps = {30000, 1001}, 389 .left_margin = 0x79, 390 .upper_margin = 0x10, 391 }, 392 { 393 .name = "pal", 394 .timings_type = VPBE_ENC_STD, 395 .std_id = V4L2_STD_PAL, 396 .interlaced = 1, 397 .xres = 720, 398 .yres = 576, 399 .aspect = {54, 59}, 400 .fps = {25, 1}, 401 .left_margin = 0x7E, 402 .upper_margin = 0x16, 403 }, 404}; 405 406/* venc dv timings */ 407static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = { 408 { 409 .name = "480p59_94", 410 .timings_type = VPBE_ENC_DV_TIMINGS, 411 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, 412 .interlaced = 0, 413 .xres = 720, 414 .yres = 480, 415 .aspect = {1, 1}, 416 .fps = {5994, 100}, 417 .left_margin = 0x8F, 418 .upper_margin = 0x2D, 419 }, 420 { 421 .name = "576p50", 422 .timings_type = VPBE_ENC_DV_TIMINGS, 423 .dv_timings = V4L2_DV_BT_CEA_720X576P50, 424 .interlaced = 0, 425 .xres = 720, 426 .yres = 576, 427 .aspect = {1, 1}, 428 .fps = {50, 1}, 429 .left_margin = 0x8C, 430 .upper_margin = 0x36, 431 }, 432 { 433 .name = "720p60", 434 .timings_type = VPBE_ENC_DV_TIMINGS, 435 .dv_timings = V4L2_DV_BT_CEA_1280X720P60, 436 .interlaced = 0, 437 .xres = 1280, 438 .yres = 720, 439 .aspect = {1, 1}, 440 .fps = {60, 1}, 441 .left_margin = 0x117, 442 .right_margin = 70, 443 .upper_margin = 38, 444 .lower_margin = 3, 445 .hsync_len = 80, 446 .vsync_len = 5, 447 }, 448 { 449 .name = "1080i60", 450 .timings_type = VPBE_ENC_DV_TIMINGS, 451 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60, 452 .interlaced = 1, 453 .xres = 1920, 454 .yres = 1080, 455 .aspect = {1, 1}, 456 .fps = {30, 1}, 457 .left_margin = 0xc9, 458 .right_margin = 80, 459 .upper_margin = 30, 460 .lower_margin = 3, 461 .hsync_len = 88, 462 .vsync_len = 5, 463 }, 464}; 465 466#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) 467 468/* 469 * The outputs available from VPBE + ecnoders. Keep the 470 * the order same as that of encoders. First those from venc followed by that 471 * from encoders. Index in the output refers to index on a particular 472 * encoder.Driver uses this index to pass it to encoder when it supports more 473 * than one output. Application uses index of the array to set an output. 474 */ 475static struct vpbe_output dm365evm_vpbe_outputs[] = { 476 { 477 .output = { 478 .index = 0, 479 .name = "Composite", 480 .type = V4L2_OUTPUT_TYPE_ANALOG, 481 .std = VENC_STD_ALL, 482 .capabilities = V4L2_OUT_CAP_STD, 483 }, 484 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, 485 .default_mode = "ntsc", 486 .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing), 487 .modes = dm365evm_enc_std_timing, 488 .if_params = V4L2_MBUS_FMT_FIXED, 489 }, 490 { 491 .output = { 492 .index = 1, 493 .name = "Component", 494 .type = V4L2_OUTPUT_TYPE_ANALOG, 495 .capabilities = V4L2_OUT_CAP_DV_TIMINGS, 496 }, 497 .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, 498 .default_mode = "480p59_94", 499 .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing), 500 .modes = dm365evm_enc_preset_timing, 501 .if_params = V4L2_MBUS_FMT_FIXED, 502 }, 503}; 504 505/* 506 * Amplifiers on the board 507 */ 508static struct ths7303_platform_data ths7303_pdata = { 509 .ch_1 = 3, 510 .ch_2 = 3, 511 .ch_3 = 3, 512}; 513 514static struct amp_config_info vpbe_amp = { 515 .module_name = "ths7303", 516 .is_i2c = 1, 517 .board_info = { 518 I2C_BOARD_INFO("ths7303", 0x2c), 519 .platform_data = &ths7303_pdata, 520 } 521}; 522 523static struct vpbe_config dm365evm_display_cfg = { 524 .module_name = "dm365-vpbe-display", 525 .i2c_adapter_id = 1, 526 .amp = &vpbe_amp, 527 .osd = { 528 .module_name = DM365_VPBE_OSD_SUBDEV_NAME, 529 }, 530 .venc = { 531 .module_name = DM365_VPBE_VENC_SUBDEV_NAME, 532 }, 533 .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs), 534 .outputs = dm365evm_vpbe_outputs, 535}; 536 537static void __init evm_init_i2c(void) 538{ 539 davinci_init_i2c(&i2c_pdata); 540 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); 541} 542 543static struct platform_device *dm365_evm_nand_devices[] __initdata = { 544 &davinci_nand_device, 545}; 546 547static inline int have_leds(void) 548{ 549#ifdef CONFIG_LEDS_CLASS 550 return 1; 551#else 552 return 0; 553#endif 554} 555 556struct cpld_led { 557 struct led_classdev cdev; 558 u8 mask; 559}; 560 561static const struct { 562 const char *name; 563 const char *trigger; 564} cpld_leds[] = { 565 { "dm365evm::ds2", }, 566 { "dm365evm::ds3", }, 567 { "dm365evm::ds4", }, 568 { "dm365evm::ds5", }, 569 { "dm365evm::ds6", "nand-disk", }, 570 { "dm365evm::ds7", "mmc1", }, 571 { "dm365evm::ds8", "mmc0", }, 572 { "dm365evm::ds9", "heartbeat", }, 573}; 574 575static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) 576{ 577 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); 578 u8 reg = __raw_readb(cpld + CPLD_LEDS); 579 580 if (b != LED_OFF) 581 reg &= ~led->mask; 582 else 583 reg |= led->mask; 584 __raw_writeb(reg, cpld + CPLD_LEDS); 585} 586 587static enum led_brightness cpld_led_get(struct led_classdev *cdev) 588{ 589 struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); 590 u8 reg = __raw_readb(cpld + CPLD_LEDS); 591 592 return (reg & led->mask) ? LED_OFF : LED_FULL; 593} 594 595static int __init cpld_leds_init(void) 596{ 597 int i; 598 599 if (!have_leds() || !cpld) 600 return 0; 601 602 /* setup LEDs */ 603 __raw_writeb(0xff, cpld + CPLD_LEDS); 604 for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { 605 struct cpld_led *led; 606 607 led = kzalloc(sizeof(*led), GFP_KERNEL); 608 if (!led) 609 break; 610 611 led->cdev.name = cpld_leds[i].name; 612 led->cdev.brightness_set = cpld_led_set; 613 led->cdev.brightness_get = cpld_led_get; 614 led->cdev.default_trigger = cpld_leds[i].trigger; 615 led->mask = BIT(i); 616 617 if (led_classdev_register(NULL, &led->cdev) < 0) { 618 kfree(led); 619 break; 620 } 621 } 622 623 return 0; 624} 625/* run after subsys_initcall() for LEDs */ 626fs_initcall(cpld_leds_init); 627 628 629static void __init evm_init_cpld(void) 630{ 631 u8 mux, resets; 632 const char *label; 633 struct clk *aemif_clk; 634 635 /* Make sure we can configure the CPLD through CS1. Then 636 * leave it on for later access to MMC and LED registers. 637 */ 638 aemif_clk = clk_get(NULL, "aemif"); 639 if (IS_ERR(aemif_clk)) 640 return; 641 clk_prepare_enable(aemif_clk); 642 643 if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, 644 "cpld") == NULL) 645 goto fail; 646 cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); 647 if (!cpld) { 648 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, 649 SECTION_SIZE); 650fail: 651 pr_err("ERROR: can't map CPLD\n"); 652 clk_disable_unprepare(aemif_clk); 653 return; 654 } 655 656 /* External muxing for some signals */ 657 mux = 0; 658 659 /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). 660 * NOTE: SW4 bus width setting must match! 661 */ 662 if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { 663 /* external keypad mux */ 664 mux |= BIT(7); 665 666 platform_add_devices(dm365_evm_nand_devices, 667 ARRAY_SIZE(dm365_evm_nand_devices)); 668 } else { 669 /* no OneNAND support yet */ 670 } 671 672 /* Leave external chips in reset when unused. */ 673 resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); 674 675 /* Static video input config with SN74CBT16214 1-of-3 mux: 676 * - port b1 == tvp7002 (mux lowbits == 1 or 6) 677 * - port b2 == imager (mux lowbits == 2 or 7) 678 * - port b3 == tvp5146 (mux lowbits == 5) 679 * 680 * Runtime switching could work too, with limitations. 681 */ 682 if (have_imager()) { 683 label = "HD imager"; 684 mux |= 2; 685 686 /* externally mux MMC1/ENET/AIC33 to imager */ 687 mux |= BIT(6) | BIT(5) | BIT(3); 688 } else { 689 struct davinci_soc_info *soc_info = &davinci_soc_info; 690 691 /* we can use MMC1 ... */ 692 dm365evm_mmc_configure(); 693 davinci_setup_mmc(1, &dm365evm_mmc_config); 694 695 /* ... and ENET ... */ 696 dm365evm_emac_configure(); 697 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID; 698 resets &= ~BIT(3); 699 700 /* ... and AIC33 */ 701 resets &= ~BIT(1); 702 703 if (have_tvp7002()) { 704 mux |= 1; 705 resets &= ~BIT(2); 706 label = "tvp7002 HD"; 707 } else { 708 /* default to tvp5146 */ 709 mux |= 5; 710 resets &= ~BIT(0); 711 label = "tvp5146 SD"; 712 } 713 } 714 __raw_writeb(mux, cpld + CPLD_MUX); 715 __raw_writeb(resets, cpld + CPLD_RESETS); 716 pr_info("EVM: %s video input\n", label); 717 718 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ 719} 720 721static void __init dm365_evm_map_io(void) 722{ 723 dm365_init(); 724} 725 726static struct spi_eeprom at25640 = { 727 .byte_len = SZ_64K / 8, 728 .name = "at25640", 729 .page_size = 32, 730 .flags = EE_ADDR2, 731}; 732 733static struct spi_board_info dm365_evm_spi_info[] __initconst = { 734 { 735 .modalias = "at25", 736 .platform_data = &at25640, 737 .max_speed_hz = 10 * 1000 * 1000, 738 .bus_num = 0, 739 .chip_select = 0, 740 .mode = SPI_MODE_0, 741 }, 742}; 743 744static __init void dm365_evm_init(void) 745{ 746 int ret; 747 748 ret = dm365_gpio_register(); 749 if (ret) 750 pr_warn("%s: GPIO init failed: %d\n", __func__, ret); 751 752 evm_init_i2c(); 753 davinci_serial_init(dm365_serial_device); 754 755 dm365evm_emac_configure(); 756 dm365evm_mmc_configure(); 757 758 davinci_setup_mmc(0, &dm365evm_mmc_config); 759 760 dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg); 761 762 /* maybe setup mmc1/etc ... _after_ mmc0 */ 763 evm_init_cpld(); 764 765#ifdef CONFIG_SND_DM365_AIC3X_CODEC 766 dm365_init_asp(&dm365_evm_snd_data); 767#elif defined(CONFIG_SND_DM365_VOICE_CODEC) 768 dm365_init_vc(&dm365_evm_snd_data); 769#endif 770 dm365_init_rtc(); 771 dm365_init_ks(&dm365evm_ks_data); 772 773 dm365_init_spi0(BIT(0), dm365_evm_spi_info, 774 ARRAY_SIZE(dm365_evm_spi_info)); 775} 776 777MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") 778 .atag_offset = 0x100, 779 .map_io = dm365_evm_map_io, 780 .init_irq = davinci_irq_init, 781 .init_time = davinci_timer_init, 782 .init_machine = dm365_evm_init, 783 .init_late = davinci_init_late, 784 .dma_zone_size = SZ_128M, 785 .restart = davinci_restart, 786MACHINE_END 787 788