1/*
2 * R8A7790 processor support
3 *
4 * Copyright (C) 2013  Renesas Electronics Corporation
5 * Copyright (C) 2013  Magnus Damm
6 * Copyright (C) 2012  Renesas Solutions Corp.
7 * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
22 */
23
24#include <linux/kernel.h>
25#include <linux/platform_data/gpio-rcar.h>
26
27#include "core.h"
28#include "sh_pfc.h"
29
30#define CPU_ALL_PORT(fn, sfx)						\
31	PORT_GP_32(0, fn, sfx),						\
32	PORT_GP_32(1, fn, sfx),						\
33	PORT_GP_32(2, fn, sfx),						\
34	PORT_GP_32(3, fn, sfx),						\
35	PORT_GP_32(4, fn, sfx),						\
36	PORT_GP_32(5, fn, sfx)
37
38enum {
39	PINMUX_RESERVED = 0,
40
41	PINMUX_DATA_BEGIN,
42	GP_ALL(DATA),
43	PINMUX_DATA_END,
44
45	PINMUX_FUNCTION_BEGIN,
46	GP_ALL(FN),
47
48	/* GPSR0 */
49	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
50	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
51	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
52	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
53	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
54	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
55	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
56	FN_IP3_14_12, FN_IP3_17_15,
57
58	/* GPSR1 */
59	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
60	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
61	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
62	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
63	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
64	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
65	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
66
67	/* GPSR2 */
68	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
69	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
70	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
71	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
72	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
73	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
74	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
75
76	/* GPSR3 */
77	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
78	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
79	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
80	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
81	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
82	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
83	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
84
85	/* GPSR4 */
86	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
87	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
88	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
89	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
90	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
91	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
92	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
93	FN_IP14_15_12, FN_IP14_18_16,
94
95	/* GPSR5 */
96	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
97	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
98	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
99	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
100	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
101	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
102	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
103
104	/* IPSR0 */
105	FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
106	FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
107	FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
108	FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
109	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
110	FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
111	FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
112	FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
113	FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
114	FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
115	FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
116	FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
117	FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
118	FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
119
120	/* IPSR1 */
121	FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
122	FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
123	FN_SCIFA1_TXD_C, FN_AVB_TXD2,
124	FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
125	FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
126	FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
127	FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
128	FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
129	FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
130	FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
131	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
132	FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
133	FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
134	FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
135	FN_A0, FN_PWM3, FN_A1, FN_PWM4,
136
137	/* IPSR2 */
138	FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
139	FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
140	FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
141	FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
142	FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
143	FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
144	FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
145	FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
146	FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
147	FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
148	FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
149
150	/* IPSR3 */
151	FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
152	FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
153	FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
154	FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
155	FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
156	FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
157	FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
158	FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
159	FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
160	FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
161	FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
162	FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
163	FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
164
165	/* IPSR4 */
166	FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
167	FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
168	FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
169	FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
170	FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
171	FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
172	FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
173	FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
174	FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
175	FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
176	FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
177	FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
178	FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
179	FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
180	FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
181
182	/* IPSR5 */
183	FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
184	FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
185	FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
186	FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
187	FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
188	FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
189	FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
190	FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
191	FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
192	FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
193	FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
194	FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
195	FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
196	FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
197	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
198	FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
199	FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
200	FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
201	FN_SSI_WS78_B,
202
203	/* IPSR6 */
204	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
205	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
206	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
207	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
208	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
209	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
210	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
211	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
212	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
213	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
214	FN_I2C2_SCL_E, FN_ETH_RX_ER,
215	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
216	FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
217	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
218	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
219	FN_HRX0_E, FN_STP_ISSYNC_0_B,
220	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
221	FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
222	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
223	FN_ETH_REF_CLK, FN_HCTS0_N_E,
224	FN_STP_IVCXO27_1_B, FN_HRX0_F,
225
226	/* IPSR7 */
227	FN_ETH_MDIO, FN_HRTS0_N_E,
228	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
229	FN_HTX0_F, FN_BPFCLK_G,
230	FN_ETH_TX_EN, FN_SIM0_CLK_C,
231	FN_HRTS0_N_F, FN_ETH_MAGIC,
232	FN_SIM0_RST_C, FN_ETH_TXD0,
233	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
234	FN_ETH_MDC, FN_STP_ISD_1_B,
235	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
236	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
237	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
238	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
239	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
240	FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
241	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
242	FN_ATACS00_N, FN_AVB_RXD1,
243	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
244
245	/* IPSR8 */
246	FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
247	FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
248	FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
249	FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
250	FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
251	FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
252	FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
253	FN_VI1_CLK, FN_AVB_RX_DV,
254	FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
255	FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
256	FN_SCIFA1_RXD_D, FN_AVB_MDC,
257	FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
258	FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
259	FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
260	FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
261	FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
262	FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
263	FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
264
265	/* IPSR9 */
266	FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
267	FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
268	FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
269	FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
270	FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
271	FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
272	FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
273	FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
274	FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
275	FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
276	FN_AVB_TX_EN, FN_SD1_CMD,
277	FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
278	FN_SD1_DAT0, FN_AVB_TX_CLK,
279	FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
280	FN_SCIFB0_TXD_B, FN_SD1_DAT2,
281	FN_AVB_COL, FN_SCIFB0_CTS_N_B,
282	FN_SD1_DAT3, FN_AVB_RXD0,
283	FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
284	FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
285	FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
286	FN_VI3_CLK_B,
287
288	/* IPSR10 */
289	FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
290	FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
291	FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
292	FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
293	FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
294	FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
295	FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
296	FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
297	FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
298	FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
299	FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
300	FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
301	FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
302	FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
303	FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
304	FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
305	FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
306	FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
307	FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
308	FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
309	FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
310	FN_GLO_I0_B, FN_VI3_DATA6_B,
311
312	/* IPSR11 */
313	FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
314	FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
315	FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
316	FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
317	FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
318	FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
319	FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
320	FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
321	FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
322	FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
323	FN_FMIN_E, FN_FMIN_F,
324	FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
325	FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
326	FN_I2C2_SDA_B, FN_MLB_DAT,
327	FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
328	FN_SSI_SCK0129, FN_CAN_CLK_B,
329	FN_MOUT0,
330
331	/* IPSR12 */
332	FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
333	FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
334	FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
335	FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
336	FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
337	FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
338	FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
339	FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
340	FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
341	FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
342	FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
343	FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
344	FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
345	FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
346	FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
347	FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
348	FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
349	FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
350	FN_CAN_DEBUGOUT4,
351
352	/* IPSR13 */
353	FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
354	FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
355	FN_SCIFB1_CTS_N, FN_BPFCLK_D,
356	FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
357	FN_BPFCLK_F, FN_SSI_WS6,
358	FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
359	FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
360	FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
361	FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
362	FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
363	FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
364	FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
365	FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
366	FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
367	FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
368	FN_BPFCLK_E, FN_SSI_SDATA7_B,
369	FN_FMIN_G, FN_SSI_SDATA8,
370	FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
371	FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
372	FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
373	FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
374	FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
375
376	/* IPSR14 */
377	FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
378	FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
379	FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
380	FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
381	FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
382	FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
383	FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
384	FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
385	FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
386	FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
387	FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
388	FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
389	FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
390	FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
391	FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
392	FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
393	FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
394	FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
395	FN_HRTS0_N_C,
396
397	/* IPSR15 */
398	FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
399	FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
400	FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
401	FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
402	FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
403	FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
404	FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
405	FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
406	FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
407	FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
408	FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
409	FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
410	FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
411	FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
412	FN_DU2_DG6, FN_LCDOUT14,
413
414	/* IPSR16 */
415	FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
416	FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
417	FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
418	FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
419	FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
420	FN_TCLK1_B,
421
422	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
423	FN_SEL_SCIF1_4,
424	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
425	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
426	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
427	FN_SEL_SCIFB1_4,
428	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
429	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
430	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
431	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
432	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
433	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
434	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
435	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
436	FN_SEL_VI3_0, FN_SEL_VI3_1,
437	FN_SEL_VI2_0, FN_SEL_VI2_1,
438	FN_SEL_VI1_0, FN_SEL_VI1_1,
439	FN_SEL_VI0_0, FN_SEL_VI0_1,
440	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
441	FN_SEL_LBS_0, FN_SEL_LBS_1,
442	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
443	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
444	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
445
446	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
447	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
448	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
449	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
450	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
451	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
452	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
453	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
454	FN_SEL_ADI_0, FN_SEL_ADI_1,
455	FN_SEL_SSP_0, FN_SEL_SSP_1,
456	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
457	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
458	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
459	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
460	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
461	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
462	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
463
464	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
465	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
466	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
467	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
468	FN_SEL_IIC2_4,
469	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
470	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
471	FN_SEL_I2C2_4,
472	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
473	PINMUX_FUNCTION_END,
474
475	PINMUX_MARK_BEGIN,
476
477	VI1_DATA7_VI1_B7_MARK,
478
479	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
480	USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
481	DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
482
483	D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
484	D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
485	VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
486	VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
487	VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
488	SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
489	VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
490	SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
491	VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
492	IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
493	I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
494	VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
495	D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
496	VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
497
498	D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
499	VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
500	SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
501	VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
502	SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
503	VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
504	D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
505	VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
506	D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
507	VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
508	SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
509	VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
510	D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
511	VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
512	A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
513
514	A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
515	PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
516	TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
517	A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
518	SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
519	A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
520	VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
521	A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
522	VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
523	A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
524	VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
525
526	A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
527	VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
528	A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
529	VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
530	A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
531	MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
532	VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
533	ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
534	ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
535	A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
536	AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
537	ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
538	VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
539
540	A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
541	A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
542	VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
543	VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
544	VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
545	VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
546	VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
547	VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
548	CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
549	VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
550	VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
551	MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
552	HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
553	VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
554	VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
555
556	EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
557	VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
558	EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
559	VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
560	INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
561	MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
562	VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
563	I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
564	CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
565	CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
566	VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
567	INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
568	VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
569	WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
570	VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
571	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
572	VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
573	MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
574	VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
575	SSI_WS78_B_MARK,
576
577	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
578	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
579	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
580	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
581	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
582	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
583	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
584	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
585	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
586	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
587	I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
588	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
589	IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
590	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
591	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
592	HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
593	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
594	RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
595	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
596	ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
597	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
598
599	ETH_MDIO_MARK, HRTS0_N_E_MARK,
600	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
601	HTX0_F_MARK, BPFCLK_G_MARK,
602	ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
603	HRTS0_N_F_MARK, ETH_MAGIC_MARK,
604	SIM0_RST_C_MARK, ETH_TXD0_MARK,
605	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
606	ETH_MDC_MARK, STP_ISD_1_B_MARK,
607	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
608	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
609	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
610	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
611	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
612	PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
613	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
614	ATACS00_N_MARK, AVB_RXD1_MARK,
615	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
616
617	VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
618	VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
619	AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
620	AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
621	AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
622	AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
623	VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
624	VI1_CLK_MARK, AVB_RX_DV_MARK,
625	VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
626	AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
627	SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
628	VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
629	VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
630	AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
631	AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
632	AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
633	SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
634	SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
635
636	SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
637	SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
638	SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
639	SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
640	SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
641	GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
642	I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
643	MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
644	GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
645	I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
646	AVB_TX_EN_MARK, SD1_CMD_MARK,
647	AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
648	SD1_DAT0_MARK, AVB_TX_CLK_MARK,
649	SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
650	SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
651	AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
652	SD1_DAT3_MARK, AVB_RXD0_MARK,
653	SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
654	TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
655	IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
656	VI3_CLK_B_MARK,
657
658	SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
659	GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
660	SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
661	VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
662	VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
663	VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
664	TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
665	SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
666	VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
667	TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
668	SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
669	VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
670	TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
671	SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
672	VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
673	GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
674	MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
675	HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
676	VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
677	TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
678	VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
679	GLO_I0_B_MARK, VI3_DATA6_B_MARK,
680
681	SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
682	GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
683	TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
684	SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
685	MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
686	SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
687	MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
688	SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
689	VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
690	MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
691	FMIN_E_MARK, FMIN_F_MARK,
692	MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
693	MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
694	I2C2_SDA_B_MARK, MLB_DAT_MARK,
695	SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
696	SSI_SCK0129_MARK, CAN_CLK_B_MARK,
697	MOUT0_MARK,
698
699	SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
700	SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
701	SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
702	SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
703	SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
704	MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
705	STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
706	CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
707	SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
708	SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
709	MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
710	SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
711	MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
712	SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
713	CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
714	IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
715	CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
716	IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
717	CAN_DEBUGOUT4_MARK,
718
719	SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
720	LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
721	SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
722	DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
723	BPFCLK_F_MARK, SSI_WS6_MARK,
724	SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
725	LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
726	FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
727	CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
728	SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
729	CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
730	SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
731	LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
732	STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
733	TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
734	BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
735	FMIN_G_MARK, SSI_SDATA8_MARK,
736	STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
737	CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
738	STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
739	SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
740	SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
741
742	AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
743	DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
744	REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
745	MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
746	I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
747	DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
748	TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
749	HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
750	LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
751	SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
752	MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
753	SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
754	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
755	SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
756	LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
757	CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
758	SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
759	MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
760	HRTS0_N_C_MARK,
761
762	SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
763	LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
764	TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
765	SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
766	IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
767	DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
768	DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
769	LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
770	LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
771	LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
772	DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
773	SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
774	HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
775	DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
776	DU2_DG6_MARK, LCDOUT14_MARK,
777
778	MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
779	DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
780	MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
781	ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
782	USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
783	TCLK1_B_MARK,
784
785	IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
786	IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
787	PINMUX_MARK_END,
788};
789
790static const u16 pinmux_data[] = {
791	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
792
793	PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
794	PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
795	PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
796	PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
797	PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
798	PINMUX_DATA(AVS1_MARK, FN_AVS1),
799	PINMUX_DATA(AVS2_MARK, FN_AVS2),
800	PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
801	PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
802
803	PINMUX_IPSR_DATA(IP0_2_0, D0),
804	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
805	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
806	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
807	PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
808	PINMUX_IPSR_DATA(IP0_5_3, D1),
809	PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
810	PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
811	PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
812	PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
813	PINMUX_IPSR_DATA(IP0_8_6, D2),
814	PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
815	PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
816	PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
817	PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
818	PINMUX_IPSR_DATA(IP0_11_9, D3),
819	PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
820	PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
821	PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
822	PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
823	PINMUX_IPSR_DATA(IP0_15_12, D4),
824	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
825	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
826	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
827	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
828	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
829	PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
830	PINMUX_IPSR_DATA(IP0_19_16, D5),
831	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
832	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
833	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
834	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
835	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
836	PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
837	PINMUX_IPSR_DATA(IP0_22_20, D6),
838	PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
839	PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
840	PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
841	PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
842	PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
843	PINMUX_IPSR_DATA(IP0_26_23, D7),
844	PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
845	PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
846	PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
847	PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
848	PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
849	PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
850	PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
851	PINMUX_IPSR_DATA(IP0_30_27, D8),
852	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
853	PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
854	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
855	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
856	PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
857
858	PINMUX_IPSR_DATA(IP1_3_0, D9),
859	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
860	PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
861	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
862	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
863	PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
864	PINMUX_IPSR_DATA(IP1_7_4, D10),
865	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
866	PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
867	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
868	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
869	PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
870	PINMUX_IPSR_DATA(IP1_11_8, D11),
871	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
872	PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
873	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
874	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
875	PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
876	PINMUX_IPSR_DATA(IP1_14_12, D12),
877	PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
878	PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
879	PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
880	PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
881	PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
882	PINMUX_IPSR_DATA(IP1_17_15, D13),
883	PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
884	PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
885	PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
886	PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
887	PINMUX_IPSR_DATA(IP1_21_18, D14),
888	PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
889	PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
890	PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
891	PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
892	PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
893	PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
894	PINMUX_IPSR_DATA(IP1_25_22, D15),
895	PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
896	PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
897	PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
898	PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
899	PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
900	PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
901	PINMUX_IPSR_DATA(IP1_27_26, A0),
902	PINMUX_IPSR_DATA(IP1_27_26, PWM3),
903	PINMUX_IPSR_DATA(IP1_29_28, A1),
904	PINMUX_IPSR_DATA(IP1_29_28, PWM4),
905
906	PINMUX_IPSR_DATA(IP2_2_0, A2),
907	PINMUX_IPSR_DATA(IP2_2_0, PWM5),
908	PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
909	PINMUX_IPSR_DATA(IP2_5_3, A3),
910	PINMUX_IPSR_DATA(IP2_5_3, PWM6),
911	PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
912	PINMUX_IPSR_DATA(IP2_8_6, A4),
913	PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
914	PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
915	PINMUX_IPSR_DATA(IP2_11_9, A5),
916	PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
917	PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
918	PINMUX_IPSR_DATA(IP2_14_12, A6),
919	PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
920	PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
921	PINMUX_IPSR_DATA(IP2_17_15, A7),
922	PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
923	PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
924	PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
925	PINMUX_IPSR_DATA(IP2_21_18, A8),
926	PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
927	PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
928	PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
929	PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
930	PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
931	PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
932	PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
933	PINMUX_IPSR_DATA(IP2_25_22, A9),
934	PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
935	PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
936	PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
937	PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
938	PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
939	PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
940	PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
941	PINMUX_IPSR_DATA(IP2_28_26, A10),
942	PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
943	PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
944	PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
945	PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
946	PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
947
948	PINMUX_IPSR_DATA(IP3_3_0, A11),
949	PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
950	PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
951	PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
952	PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
953	PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
954	PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
955	PINMUX_IPSR_DATA(IP3_7_4, A12),
956	PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
957	PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
958	PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
959	PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
960	PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
961	PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
962	PINMUX_IPSR_DATA(IP3_11_8, A13),
963	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
964	PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
965	PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
966	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
967	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
968	PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
969	PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
970	PINMUX_IPSR_DATA(IP3_14_12, A14),
971	PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
972	PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
973	PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
974	PINMUX_IPSR_DATA(IP3_17_15, A15),
975	PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
976	PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
977	PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
978	PINMUX_IPSR_DATA(IP3_19_18, A16),
979	PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
980	PINMUX_IPSR_DATA(IP3_22_20, A17),
981	PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
982	PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
983	PINMUX_IPSR_DATA(IP3_25_23, A18),
984	PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
985	PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
986	PINMUX_IPSR_DATA(IP3_28_26, A19),
987	PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
988	PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
989	PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
990	PINMUX_IPSR_DATA(IP3_31_29, A20),
991	PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
992	PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
993	PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
994	PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
995
996	PINMUX_IPSR_DATA(IP4_2_0, A21),
997	PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
998	PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
999	PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1000	PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1001	PINMUX_IPSR_DATA(IP4_5_3, A22),
1002	PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1003	PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1004	PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1005	PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1006	PINMUX_IPSR_DATA(IP4_8_6, A23),
1007	PINMUX_IPSR_DATA(IP4_8_6, IO2),
1008	PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1009	PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1010	PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1011	PINMUX_IPSR_DATA(IP4_11_9, A24),
1012	PINMUX_IPSR_DATA(IP4_11_9, IO3),
1013	PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1014	PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1015	PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1016	PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1017	PINMUX_IPSR_DATA(IP4_14_12, A25),
1018	PINMUX_IPSR_DATA(IP4_14_12, SSL),
1019	PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1020	PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1021	PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1022	PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1023	PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1024	PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1025	PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1026	PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1027	PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1028	PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1029	PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1030	PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1031	PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1032	PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1033	PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1034	PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1035	PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1036	PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1037	PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1038	PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1039	PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1040	PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1041	PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1042	PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1043	PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1044	PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1045	PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1046	PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1047	PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1048	PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1049	PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1050	PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1051	PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1052	PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1053	PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1054
1055	PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1056	PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1057	PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1058	PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1059	PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1060	PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1061	PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
1062	PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1063	PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1064	PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1065	PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1066	PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1067	PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1068	PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1069	PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1070	PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1071	PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1072	PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1073	PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1074	PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1075	PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1076	PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1077	PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1078	PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1079	PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1080	PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1081	PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1082	PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1083	PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1084	PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1085	PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1086	PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1087	PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1088	PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1089	PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1090	PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1091	PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1092	PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1093	PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1094	PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1095	PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1096	PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1097	PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1098	PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1099	PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1100	PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1101	PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1102	PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1103	PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1104	PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1105	PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1106	PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1107	PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1108	PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1109	PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1110	PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1111	PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1112	PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1113	PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1114	PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1115	PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1116	PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1117	PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1118	PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1119	PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1120	PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1121
1122	PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1123	PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1124	PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1125	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1126	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1127	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1128	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1129	PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1130	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1131	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1132	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1133	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1134	PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1135	PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1136	PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1137	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1138	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1139	PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1140	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1141	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1142	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1143	PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1144	PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1145	PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1146	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1147	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1148	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1149	PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1150	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1151	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1152	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1153	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1154	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1155	PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1156	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1157	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1158	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1159	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1160	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1161	PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1162	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1163	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1164	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1165	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1166	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1167	PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1168	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1169	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1170	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1171	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1172	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1173	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1174	PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1175	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1176	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1177	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1178	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1179	PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1180	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1181	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1182	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1183
1184	PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1185	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1186	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1187	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1188	PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1189	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1190	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
1191	PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1192	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1193	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1194	PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1195	PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1196	PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1197	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1198	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1199	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1200	PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1201	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1202	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1203	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1204	PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1205	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1206	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1207	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1208	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1209	PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1210	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1211	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1212	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1213	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1214	PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1215	PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1216	PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1217	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1218	PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1219	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
1220	PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
1221	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1222	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1223	PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1224	PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1225	PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1226	PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1227	PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1228	PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1229
1230	PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1231	PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1232	PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1233	PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1234	PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1235	PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1236	PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1237	PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1238	PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1239	PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1240	PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1241	PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1242	PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1243	PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1244	PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1245	PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1246	PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1247	PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1248	PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1249	PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1250	PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1251	PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1252	PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1253	PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1254	PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1255	PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1256	PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1257	PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1258	PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1259	PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1260	PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1261	PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1262	PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1263	PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1264	PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1265	PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1266	PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1267	PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
1268	PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1269	PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1270	PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1271	PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1272	PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1273	PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1274	PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1275
1276	PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1277	PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1278	PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1279	PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1280	PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1281	PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1282	PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1283	PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1284	PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1285	PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1286	PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1287	PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1288	PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1289	PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1290	PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1291	PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1292	PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1293	PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1294	PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1295	PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1296	PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1297	PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1298	PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1299	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1300	PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1301	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1302	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1303	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1304	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1305	PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1306	PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1307	PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1308	PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1309	PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1310	PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1311	PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1312	PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1313	PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1314	PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1315	PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1316	PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1317	PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1318	PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1319	PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1320	PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1321	PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1322	PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1323	PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1324	PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1325	PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1326	PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1327	PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1328	PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1329	PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1330	PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1331	PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1332	PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1333
1334	PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1335	PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1336	PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1337	PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1338	PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1339	PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1340	PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1341	PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1342	PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1343	PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1344	PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1345	PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1346	PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1347	PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1348	PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1349	PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1350	PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1351	PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1352	PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1353	PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1354	PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1355	PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1356	PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1357	PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1358	PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1359	PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1360	PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1361	PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1362	PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1363	PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1364	PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1365	PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1366	PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1367	PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1368	PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1369	PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1370	PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1371	PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1372	PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1373	PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1374	PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1375	PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1376	PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1377	PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1378	PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1379	PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1380	PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1381	PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1382	PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1383	PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1384	PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1385	PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1386	PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1387	PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1388	PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1389	PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1390	PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1391	PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1392	PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1393	PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1394	PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1395	PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1396	PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1397	PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1398	PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1399	PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1400	PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1401	PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1402	PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1403
1404	PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1405	PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1406	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1407	PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1408	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1409	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1410	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1411	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1412	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1413	PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1414	PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1415	PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1416	PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1417	PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1418	PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1419	PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1420	PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1421	PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1422	PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1423	PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1424	PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1425	PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1426	PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1427	PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1428	PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1429	PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1430	PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1431	PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1432	PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1433	PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1434	PINMUX_IPSR_DATA(IP11_17_15, VSP),
1435	PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1436	PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1437	PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1438	PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1439	PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1440	PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1441	PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1442	PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1443	PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1444	PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1445	PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1446	PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1447	PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1448	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1449	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1450	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1451	PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1452	PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1453	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1454	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1455	PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1456	PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1457	PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1458	PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1459
1460	PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1461	PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1462	PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1463	PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1464	PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1465	PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1466	PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1467	PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1468	PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1469	PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1470	PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1471	PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
1472	PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1473	PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1474	PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1475	PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1476	PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1477	PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1478	PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1479	PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1480	PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1481	PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1482	PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1483	PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1484	PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1485	PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1486	PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1487	PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1488	PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1489	PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1490	PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1491	PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1492	PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1493	PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1494	PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1495	PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1496	PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1497	PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1498	PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1499	PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1500	PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1501	PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1502	PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1503	PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1504	PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1505	PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1506	PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1507	PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1508	PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1509	PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1510	PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1511	PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1512	PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1513	PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1514	PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1515	PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1516
1517	PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1518	PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1519	PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1520	PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1521	PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1522	PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1523	PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1524	PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1525	PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1526	PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1527	PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1528	PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1529	PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1530	PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1531	PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1532	PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1533	PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1534	PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1535	PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1536	PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1537	PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1538	PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1539	PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1540	PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1541	PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1542	PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1543	PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1544	PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1545	PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1546	PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1547	PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1548	PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1549	PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1550	PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1551	PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1552	PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1553	PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1554	PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1555	PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1556	PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1557	PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1558	PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1559	PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1560	PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1561	PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1562	PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1563	PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1564	PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1565	PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1566	PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1567	PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1568	PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1569	PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1570	PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1571	PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1572	PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1573	PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1574	PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1575	PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1576	PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1577	PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1578	PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1579	PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1580
1581	PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1582	PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1583	PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1584	PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1585	PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1586	PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1587	PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1588	PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1589	PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1590	PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1591	PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1592	PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1593	PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1594	PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1595	PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1596	PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1597	PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1598	PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1599	PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1600	PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1601	PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1602	PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1603	PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1604	PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1605	PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1606	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1607	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1608	PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
1609	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1610	PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1611	PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1612	PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
1613	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1614	PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1615	PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1616	PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1617	PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
1618	PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1619	PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1620	PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1621	PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1622	PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1623	PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1624	PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1625	PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1626	PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1627	PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1628	PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1629	PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1630	PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1631	PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1632	PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1633	PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1634	PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1635	PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1636	PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1637	PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1638	PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1639	PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1640	PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
1641	PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1642	PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1643	PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1644	PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1645
1646	PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1647	PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1648	PINMUX_IPSR_DATA(IP15_2_0, SCK2),
1649	PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1650	PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1651	PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1652	PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1653	PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1654	PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1655	PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
1656	PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1657	PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1658	PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1659	PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1660	PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1661	PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1662	PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
1663	PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1664	PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1665	PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1666	PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1667	PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1668	PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1669	PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1670	PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1671	PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1672	PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1673	PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1674	PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1675	PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1676	PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1677	PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1678	PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1679	PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1680	PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1681	PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1682	PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1683	PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1684	PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1685	PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1686	PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1687	PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1688	PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1689	PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1690	PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1691	PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1692	PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1693	PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1694	PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1695	PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1696	PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1697	PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1698	PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1699	PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1700	PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1701	PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1702	PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1703	PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1704	PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1705	PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1706
1707	PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1708	PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1709	PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1710	PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1711	PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1712	PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1713	PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1714	PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1715	PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1716	PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1717	PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1718	PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1719	PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1720	PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1721	PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1722	PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1723	PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1724	PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1725
1726	PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1727	PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1728	PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1729	PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1730
1731	PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1732	PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1733	PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1734	PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1735};
1736
1737/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1738#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1739#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1740#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1741
1742static const struct sh_pfc_pin pinmux_pins[] = {
1743	PINMUX_GPIO_GP_ALL(),
1744
1745	/* Pins not associated with a GPIO port */
1746	SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1747	SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
1748	SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1749	SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1750};
1751
1752/* - AUDIO CLOCK ------------------------------------------------------------ */
1753static const unsigned int audio_clk_a_pins[] = {
1754	/* CLK A */
1755	RCAR_GP_PIN(4, 25),
1756};
1757static const unsigned int audio_clk_a_mux[] = {
1758	AUDIO_CLKA_MARK,
1759};
1760static const unsigned int audio_clk_b_pins[] = {
1761	/* CLK B */
1762	RCAR_GP_PIN(4, 26),
1763};
1764static const unsigned int audio_clk_b_mux[] = {
1765	AUDIO_CLKB_MARK,
1766};
1767static const unsigned int audio_clk_c_pins[] = {
1768	/* CLK C */
1769	RCAR_GP_PIN(5, 27),
1770};
1771static const unsigned int audio_clk_c_mux[] = {
1772	AUDIO_CLKC_MARK,
1773};
1774static const unsigned int audio_clkout_pins[] = {
1775	/* CLK OUT */
1776	RCAR_GP_PIN(5, 16),
1777};
1778static const unsigned int audio_clkout_mux[] = {
1779	AUDIO_CLKOUT_MARK,
1780};
1781static const unsigned int audio_clkout_b_pins[] = {
1782	/* CLK OUT B */
1783	RCAR_GP_PIN(0, 23),
1784};
1785static const unsigned int audio_clkout_b_mux[] = {
1786	AUDIO_CLKOUT_B_MARK,
1787};
1788static const unsigned int audio_clkout_c_pins[] = {
1789	/* CLK OUT C */
1790	RCAR_GP_PIN(5, 27),
1791};
1792static const unsigned int audio_clkout_c_mux[] = {
1793	AUDIO_CLKOUT_C_MARK,
1794};
1795static const unsigned int audio_clkout_d_pins[] = {
1796	/* CLK OUT D */
1797	RCAR_GP_PIN(5, 20),
1798};
1799static const unsigned int audio_clkout_d_mux[] = {
1800	AUDIO_CLKOUT_D_MARK,
1801};
1802/* - DU RGB ----------------------------------------------------------------- */
1803static const unsigned int du_rgb666_pins[] = {
1804	/* R[7:2], G[7:2], B[7:2] */
1805	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1806	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1807	RCAR_GP_PIN(5, 4),  RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1808	RCAR_GP_PIN(5, 7),  RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1809	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1810	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),  RCAR_GP_PIN(5, 8),
1811};
1812static const unsigned int du_rgb666_mux[] = {
1813	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1814	DU2_DR3_MARK, DU2_DR2_MARK,
1815	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1816	DU2_DG3_MARK, DU2_DG2_MARK,
1817	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1818	DU2_DB3_MARK, DU2_DB2_MARK,
1819};
1820static const unsigned int du_rgb888_pins[] = {
1821	/* R[7:0], G[7:0], B[7:0] */
1822	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1823	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1824	RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1825	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1826	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1827	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1828	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1829	RCAR_GP_PIN(5, 8),  RCAR_GP_PIN(5, 6),  RCAR_GP_PIN(5, 5),
1830};
1831static const unsigned int du_rgb888_mux[] = {
1832	DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1833	DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1834	DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1835	DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1836	DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1837	DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1838};
1839static const unsigned int du_clk_out_0_pins[] = {
1840	/* CLKOUT */
1841	RCAR_GP_PIN(5, 2),
1842};
1843static const unsigned int du_clk_out_0_mux[] = {
1844	DU0_DOTCLKOUT_MARK
1845};
1846static const unsigned int du_clk_out_1_pins[] = {
1847	/* CLKOUT */
1848	RCAR_GP_PIN(5, 3),
1849};
1850static const unsigned int du_clk_out_1_mux[] = {
1851	DU1_DOTCLKOUT_MARK
1852};
1853static const unsigned int du_sync_0_pins[] = {
1854	/* VSYNC, HSYNC, DISP */
1855	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1856};
1857static const unsigned int du_sync_0_mux[] = {
1858	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1859	DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1860};
1861static const unsigned int du_sync_1_pins[] = {
1862	/* VSYNC, HSYNC, DISP */
1863	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1864};
1865static const unsigned int du_sync_1_mux[] = {
1866	DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1867	DU2_DISP_MARK
1868};
1869static const unsigned int du_cde_pins[] = {
1870	/* CDE */
1871	RCAR_GP_PIN(5, 17),
1872};
1873static const unsigned int du_cde_mux[] = {
1874	DU2_CDE_MARK,
1875};
1876/* - DU0 -------------------------------------------------------------------- */
1877static const unsigned int du0_clk_in_pins[] = {
1878	/* CLKIN */
1879	RCAR_GP_PIN(5, 26),
1880};
1881static const unsigned int du0_clk_in_mux[] = {
1882	DU_DOTCLKIN0_MARK
1883};
1884/* - DU1 -------------------------------------------------------------------- */
1885static const unsigned int du1_clk_in_pins[] = {
1886	/* CLKIN */
1887	RCAR_GP_PIN(5, 27),
1888};
1889static const unsigned int du1_clk_in_mux[] = {
1890	DU_DOTCLKIN1_MARK,
1891};
1892/* - DU2 -------------------------------------------------------------------- */
1893static const unsigned int du2_clk_in_pins[] = {
1894	/* CLKIN */
1895	RCAR_GP_PIN(5, 28),
1896};
1897static const unsigned int du2_clk_in_mux[] = {
1898	DU_DOTCLKIN2_MARK,
1899};
1900/* - ETH -------------------------------------------------------------------- */
1901static const unsigned int eth_link_pins[] = {
1902	/* LINK */
1903	RCAR_GP_PIN(2, 22),
1904};
1905static const unsigned int eth_link_mux[] = {
1906	ETH_LINK_MARK,
1907};
1908static const unsigned int eth_magic_pins[] = {
1909	/* MAGIC */
1910	RCAR_GP_PIN(2, 27),
1911};
1912static const unsigned int eth_magic_mux[] = {
1913	ETH_MAGIC_MARK,
1914};
1915static const unsigned int eth_mdio_pins[] = {
1916	/* MDC, MDIO */
1917	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1918};
1919static const unsigned int eth_mdio_mux[] = {
1920	ETH_MDC_MARK, ETH_MDIO_MARK,
1921};
1922static const unsigned int eth_rmii_pins[] = {
1923	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1924	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1925	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1926	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1927};
1928static const unsigned int eth_rmii_mux[] = {
1929	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1930	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1931};
1932/* - HSCIF0 ----------------------------------------------------------------- */
1933static const unsigned int hscif0_data_pins[] = {
1934	/* RX, TX */
1935	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1936};
1937static const unsigned int hscif0_data_mux[] = {
1938	HRX0_MARK, HTX0_MARK,
1939};
1940static const unsigned int hscif0_clk_pins[] = {
1941	/* SCK */
1942	RCAR_GP_PIN(5, 7),
1943};
1944static const unsigned int hscif0_clk_mux[] = {
1945	HSCK0_MARK,
1946};
1947static const unsigned int hscif0_ctrl_pins[] = {
1948	/* RTS, CTS */
1949	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1950};
1951static const unsigned int hscif0_ctrl_mux[] = {
1952	HRTS0_N_MARK, HCTS0_N_MARK,
1953};
1954static const unsigned int hscif0_data_b_pins[] = {
1955	/* RX, TX */
1956	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
1957};
1958static const unsigned int hscif0_data_b_mux[] = {
1959	HRX0_B_MARK, HTX0_B_MARK,
1960};
1961static const unsigned int hscif0_ctrl_b_pins[] = {
1962	/* RTS, CTS */
1963	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
1964};
1965static const unsigned int hscif0_ctrl_b_mux[] = {
1966	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1967};
1968static const unsigned int hscif0_data_c_pins[] = {
1969	/* RX, TX */
1970	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
1971};
1972static const unsigned int hscif0_data_c_mux[] = {
1973	HRX0_C_MARK, HTX0_C_MARK,
1974};
1975static const unsigned int hscif0_ctrl_c_pins[] = {
1976	/* RTS, CTS */
1977	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
1978};
1979static const unsigned int hscif0_ctrl_c_mux[] = {
1980	HRTS0_N_C_MARK, HCTS0_N_C_MARK,
1981};
1982static const unsigned int hscif0_data_d_pins[] = {
1983	/* RX, TX */
1984	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1985};
1986static const unsigned int hscif0_data_d_mux[] = {
1987	HRX0_D_MARK, HTX0_D_MARK,
1988};
1989static const unsigned int hscif0_ctrl_d_pins[] = {
1990	/* RTS, CTS */
1991	RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
1992};
1993static const unsigned int hscif0_ctrl_d_mux[] = {
1994	HRTS0_N_D_MARK, HCTS0_N_D_MARK,
1995};
1996static const unsigned int hscif0_data_e_pins[] = {
1997	/* RX, TX */
1998	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1999};
2000static const unsigned int hscif0_data_e_mux[] = {
2001	HRX0_E_MARK, HTX0_E_MARK,
2002};
2003static const unsigned int hscif0_ctrl_e_pins[] = {
2004	/* RTS, CTS */
2005	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2006};
2007static const unsigned int hscif0_ctrl_e_mux[] = {
2008	HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2009};
2010static const unsigned int hscif0_data_f_pins[] = {
2011	/* RX, TX */
2012	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2013};
2014static const unsigned int hscif0_data_f_mux[] = {
2015	HRX0_F_MARK, HTX0_F_MARK,
2016};
2017static const unsigned int hscif0_ctrl_f_pins[] = {
2018	/* RTS, CTS */
2019	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2020};
2021static const unsigned int hscif0_ctrl_f_mux[] = {
2022	HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2023};
2024/* - HSCIF1 ----------------------------------------------------------------- */
2025static const unsigned int hscif1_data_pins[] = {
2026	/* RX, TX */
2027	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2028};
2029static const unsigned int hscif1_data_mux[] = {
2030	HRX1_MARK, HTX1_MARK,
2031};
2032static const unsigned int hscif1_clk_pins[] = {
2033	/* SCK */
2034	RCAR_GP_PIN(4, 27),
2035};
2036static const unsigned int hscif1_clk_mux[] = {
2037	HSCK1_MARK,
2038};
2039static const unsigned int hscif1_ctrl_pins[] = {
2040	/* RTS, CTS */
2041	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2042};
2043static const unsigned int hscif1_ctrl_mux[] = {
2044	HRTS1_N_MARK, HCTS1_N_MARK,
2045};
2046static const unsigned int hscif1_data_b_pins[] = {
2047	/* RX, TX */
2048	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2049};
2050static const unsigned int hscif1_data_b_mux[] = {
2051	HRX1_B_MARK, HTX1_B_MARK,
2052};
2053static const unsigned int hscif1_clk_b_pins[] = {
2054	/* SCK */
2055	RCAR_GP_PIN(1, 28),
2056};
2057static const unsigned int hscif1_clk_b_mux[] = {
2058	HSCK1_B_MARK,
2059};
2060static const unsigned int hscif1_ctrl_b_pins[] = {
2061	/* RTS, CTS */
2062	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2063};
2064static const unsigned int hscif1_ctrl_b_mux[] = {
2065	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2066};
2067/* - I2C0 ------------------------------------------------------------------- */
2068static const unsigned int i2c0_pins[] = {
2069	/* SCL, SDA */
2070	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2071};
2072static const unsigned int i2c0_mux[] = {
2073	I2C0_SCL_MARK, I2C0_SDA_MARK,
2074};
2075/* - I2C1 ------------------------------------------------------------------- */
2076static const unsigned int i2c1_pins[] = {
2077	/* SCL, SDA */
2078	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2079};
2080static const unsigned int i2c1_mux[] = {
2081	I2C1_SCL_MARK, I2C1_SDA_MARK,
2082};
2083static const unsigned int i2c1_b_pins[] = {
2084	/* SCL, SDA */
2085	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2086};
2087static const unsigned int i2c1_b_mux[] = {
2088	I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2089};
2090static const unsigned int i2c1_c_pins[] = {
2091	/* SCL, SDA */
2092	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2093};
2094static const unsigned int i2c1_c_mux[] = {
2095	I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2096};
2097/* - I2C2 ------------------------------------------------------------------- */
2098static const unsigned int i2c2_pins[] = {
2099	/* SCL, SDA */
2100	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2101};
2102static const unsigned int i2c2_mux[] = {
2103	I2C2_SCL_MARK, I2C2_SDA_MARK,
2104};
2105static const unsigned int i2c2_b_pins[] = {
2106	/* SCL, SDA */
2107	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2108};
2109static const unsigned int i2c2_b_mux[] = {
2110	I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2111};
2112static const unsigned int i2c2_c_pins[] = {
2113	/* SCL, SDA */
2114	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2115};
2116static const unsigned int i2c2_c_mux[] = {
2117	I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2118};
2119static const unsigned int i2c2_d_pins[] = {
2120	/* SCL, SDA */
2121	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2122};
2123static const unsigned int i2c2_d_mux[] = {
2124	I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2125};
2126static const unsigned int i2c2_e_pins[] = {
2127	/* SCL, SDA */
2128	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2129};
2130static const unsigned int i2c2_e_mux[] = {
2131	I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2132};
2133/* - I2C3 ------------------------------------------------------------------- */
2134static const unsigned int i2c3_pins[] = {
2135	/* SCL, SDA */
2136	PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2137};
2138static const unsigned int i2c3_mux[] = {
2139	I2C3_SCL_MARK, I2C3_SDA_MARK,
2140};
2141/* - IIC0 (I2C4) ------------------------------------------------------------ */
2142static const unsigned int iic0_pins[] = {
2143	/* SCL, SDA */
2144	PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2145};
2146static const unsigned int iic0_mux[] = {
2147	IIC0_SCL_MARK, IIC0_SDA_MARK,
2148};
2149/* - IIC1 (I2C5) ------------------------------------------------------------ */
2150static const unsigned int iic1_pins[] = {
2151	/* SCL, SDA */
2152	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2153};
2154static const unsigned int iic1_mux[] = {
2155	IIC1_SCL_MARK, IIC1_SDA_MARK,
2156};
2157static const unsigned int iic1_b_pins[] = {
2158	/* SCL, SDA */
2159	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2160};
2161static const unsigned int iic1_b_mux[] = {
2162	IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2163};
2164static const unsigned int iic1_c_pins[] = {
2165	/* SCL, SDA */
2166	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2167};
2168static const unsigned int iic1_c_mux[] = {
2169	IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2170};
2171/* - IIC2 (I2C6) ------------------------------------------------------------ */
2172static const unsigned int iic2_pins[] = {
2173	/* SCL, SDA */
2174	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2175};
2176static const unsigned int iic2_mux[] = {
2177	IIC2_SCL_MARK, IIC2_SDA_MARK,
2178};
2179static const unsigned int iic2_b_pins[] = {
2180	/* SCL, SDA */
2181	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2182};
2183static const unsigned int iic2_b_mux[] = {
2184	IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2185};
2186static const unsigned int iic2_c_pins[] = {
2187	/* SCL, SDA */
2188	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2189};
2190static const unsigned int iic2_c_mux[] = {
2191	IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2192};
2193static const unsigned int iic2_d_pins[] = {
2194	/* SCL, SDA */
2195	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2196};
2197static const unsigned int iic2_d_mux[] = {
2198	IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2199};
2200static const unsigned int iic2_e_pins[] = {
2201	/* SCL, SDA */
2202	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2203};
2204static const unsigned int iic2_e_mux[] = {
2205	IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2206};
2207/* - IIC3 (I2C7) ------------------------------------------------------------ */
2208static const unsigned int iic3_pins[] = {
2209/* SCL, SDA */
2210	PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2211};
2212static const unsigned int iic3_mux[] = {
2213	IIC3_SCL_MARK, IIC3_SDA_MARK,
2214};
2215/* - INTC ------------------------------------------------------------------- */
2216static const unsigned int intc_irq0_pins[] = {
2217	/* IRQ */
2218	RCAR_GP_PIN(1, 25),
2219};
2220static const unsigned int intc_irq0_mux[] = {
2221	IRQ0_MARK,
2222};
2223static const unsigned int intc_irq1_pins[] = {
2224	/* IRQ */
2225	RCAR_GP_PIN(1, 27),
2226};
2227static const unsigned int intc_irq1_mux[] = {
2228	IRQ1_MARK,
2229};
2230static const unsigned int intc_irq2_pins[] = {
2231	/* IRQ */
2232	RCAR_GP_PIN(1, 29),
2233};
2234static const unsigned int intc_irq2_mux[] = {
2235	IRQ2_MARK,
2236};
2237static const unsigned int intc_irq3_pins[] = {
2238	/* IRQ */
2239	RCAR_GP_PIN(1, 23),
2240};
2241static const unsigned int intc_irq3_mux[] = {
2242	IRQ3_MARK,
2243};
2244/* - MMCIF0 ----------------------------------------------------------------- */
2245static const unsigned int mmc0_data1_pins[] = {
2246	/* D[0] */
2247	RCAR_GP_PIN(3, 18),
2248};
2249static const unsigned int mmc0_data1_mux[] = {
2250	MMC0_D0_MARK,
2251};
2252static const unsigned int mmc0_data4_pins[] = {
2253	/* D[0:3] */
2254	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2255	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2256};
2257static const unsigned int mmc0_data4_mux[] = {
2258	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2259};
2260static const unsigned int mmc0_data8_pins[] = {
2261	/* D[0:7] */
2262	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2263	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2264	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2265	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2266};
2267static const unsigned int mmc0_data8_mux[] = {
2268	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2269	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2270};
2271static const unsigned int mmc0_ctrl_pins[] = {
2272	/* CLK, CMD */
2273	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2274};
2275static const unsigned int mmc0_ctrl_mux[] = {
2276	MMC0_CLK_MARK, MMC0_CMD_MARK,
2277};
2278/* - MMCIF1 ----------------------------------------------------------------- */
2279static const unsigned int mmc1_data1_pins[] = {
2280	/* D[0] */
2281	RCAR_GP_PIN(3, 26),
2282};
2283static const unsigned int mmc1_data1_mux[] = {
2284	MMC1_D0_MARK,
2285};
2286static const unsigned int mmc1_data4_pins[] = {
2287	/* D[0:3] */
2288	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2289	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2290};
2291static const unsigned int mmc1_data4_mux[] = {
2292	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2293};
2294static const unsigned int mmc1_data8_pins[] = {
2295	/* D[0:7] */
2296	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2297	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2298	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2299	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2300};
2301static const unsigned int mmc1_data8_mux[] = {
2302	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2303	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2304};
2305static const unsigned int mmc1_ctrl_pins[] = {
2306	/* CLK, CMD */
2307	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2308};
2309static const unsigned int mmc1_ctrl_mux[] = {
2310	MMC1_CLK_MARK, MMC1_CMD_MARK,
2311};
2312/* - MSIOF0 ----------------------------------------------------------------- */
2313static const unsigned int msiof0_clk_pins[] = {
2314	/* SCK */
2315	RCAR_GP_PIN(5, 12),
2316};
2317static const unsigned int msiof0_clk_mux[] = {
2318	MSIOF0_SCK_MARK,
2319};
2320static const unsigned int msiof0_sync_pins[] = {
2321	/* SYNC */
2322	RCAR_GP_PIN(5, 13),
2323};
2324static const unsigned int msiof0_sync_mux[] = {
2325	MSIOF0_SYNC_MARK,
2326};
2327static const unsigned int msiof0_ss1_pins[] = {
2328	/* SS1 */
2329	RCAR_GP_PIN(5, 14),
2330};
2331static const unsigned int msiof0_ss1_mux[] = {
2332	MSIOF0_SS1_MARK,
2333};
2334static const unsigned int msiof0_ss2_pins[] = {
2335	/* SS2 */
2336	RCAR_GP_PIN(5, 16),
2337};
2338static const unsigned int msiof0_ss2_mux[] = {
2339	MSIOF0_SS2_MARK,
2340};
2341static const unsigned int msiof0_rx_pins[] = {
2342	/* RXD */
2343	RCAR_GP_PIN(5, 17),
2344};
2345static const unsigned int msiof0_rx_mux[] = {
2346	MSIOF0_RXD_MARK,
2347};
2348static const unsigned int msiof0_tx_pins[] = {
2349	/* TXD */
2350	RCAR_GP_PIN(5, 15),
2351};
2352static const unsigned int msiof0_tx_mux[] = {
2353	MSIOF0_TXD_MARK,
2354};
2355
2356static const unsigned int msiof0_clk_b_pins[] = {
2357	/* SCK */
2358	RCAR_GP_PIN(1, 23),
2359};
2360static const unsigned int msiof0_clk_b_mux[] = {
2361	MSIOF0_SCK_B_MARK,
2362};
2363static const unsigned int msiof0_ss1_b_pins[] = {
2364	/* SS1 */
2365	RCAR_GP_PIN(1, 12),
2366};
2367static const unsigned int msiof0_ss1_b_mux[] = {
2368	MSIOF0_SS1_B_MARK,
2369};
2370static const unsigned int msiof0_ss2_b_pins[] = {
2371	/* SS2 */
2372	RCAR_GP_PIN(1, 10),
2373};
2374static const unsigned int msiof0_ss2_b_mux[] = {
2375	MSIOF0_SS2_B_MARK,
2376};
2377static const unsigned int msiof0_rx_b_pins[] = {
2378	/* RXD */
2379	RCAR_GP_PIN(1, 29),
2380};
2381static const unsigned int msiof0_rx_b_mux[] = {
2382	MSIOF0_RXD_B_MARK,
2383};
2384static const unsigned int msiof0_tx_b_pins[] = {
2385	/* TXD */
2386	RCAR_GP_PIN(1, 28),
2387};
2388static const unsigned int msiof0_tx_b_mux[] = {
2389	MSIOF0_TXD_B_MARK,
2390};
2391/* - MSIOF1 ----------------------------------------------------------------- */
2392static const unsigned int msiof1_clk_pins[] = {
2393	/* SCK */
2394	RCAR_GP_PIN(4, 8),
2395};
2396static const unsigned int msiof1_clk_mux[] = {
2397	MSIOF1_SCK_MARK,
2398};
2399static const unsigned int msiof1_sync_pins[] = {
2400	/* SYNC */
2401	RCAR_GP_PIN(4, 9),
2402};
2403static const unsigned int msiof1_sync_mux[] = {
2404	MSIOF1_SYNC_MARK,
2405};
2406static const unsigned int msiof1_ss1_pins[] = {
2407	/* SS1 */
2408	RCAR_GP_PIN(4, 10),
2409};
2410static const unsigned int msiof1_ss1_mux[] = {
2411	MSIOF1_SS1_MARK,
2412};
2413static const unsigned int msiof1_ss2_pins[] = {
2414	/* SS2 */
2415	RCAR_GP_PIN(4, 11),
2416};
2417static const unsigned int msiof1_ss2_mux[] = {
2418	MSIOF1_SS2_MARK,
2419};
2420static const unsigned int msiof1_rx_pins[] = {
2421	/* RXD */
2422	RCAR_GP_PIN(4, 13),
2423};
2424static const unsigned int msiof1_rx_mux[] = {
2425	MSIOF1_RXD_MARK,
2426};
2427static const unsigned int msiof1_tx_pins[] = {
2428	/* TXD */
2429	RCAR_GP_PIN(4, 12),
2430};
2431static const unsigned int msiof1_tx_mux[] = {
2432	MSIOF1_TXD_MARK,
2433};
2434
2435static const unsigned int msiof1_clk_b_pins[] = {
2436	/* SCK */
2437	RCAR_GP_PIN(1, 16),
2438};
2439static const unsigned int msiof1_clk_b_mux[] = {
2440	MSIOF1_SCK_B_MARK,
2441};
2442static const unsigned int msiof1_ss1_b_pins[] = {
2443	/* SS1 */
2444	RCAR_GP_PIN(0, 18),
2445};
2446static const unsigned int msiof1_ss1_b_mux[] = {
2447	MSIOF1_SS1_B_MARK,
2448};
2449static const unsigned int msiof1_ss2_b_pins[] = {
2450	/* SS2 */
2451	RCAR_GP_PIN(0, 19),
2452};
2453static const unsigned int msiof1_ss2_b_mux[] = {
2454	MSIOF1_SS2_B_MARK,
2455};
2456static const unsigned int msiof1_rx_b_pins[] = {
2457	/* RXD */
2458	RCAR_GP_PIN(1, 17),
2459};
2460static const unsigned int msiof1_rx_b_mux[] = {
2461	MSIOF1_RXD_B_MARK,
2462};
2463static const unsigned int msiof1_tx_b_pins[] = {
2464	/* TXD */
2465	RCAR_GP_PIN(0, 20),
2466};
2467static const unsigned int msiof1_tx_b_mux[] = {
2468	MSIOF1_TXD_B_MARK,
2469};
2470/* - MSIOF2 ----------------------------------------------------------------- */
2471static const unsigned int msiof2_clk_pins[] = {
2472	/* SCK */
2473	RCAR_GP_PIN(0, 27),
2474};
2475static const unsigned int msiof2_clk_mux[] = {
2476	MSIOF2_SCK_MARK,
2477};
2478static const unsigned int msiof2_sync_pins[] = {
2479	/* SYNC */
2480	RCAR_GP_PIN(0, 26),
2481};
2482static const unsigned int msiof2_sync_mux[] = {
2483	MSIOF2_SYNC_MARK,
2484};
2485static const unsigned int msiof2_ss1_pins[] = {
2486	/* SS1 */
2487	RCAR_GP_PIN(0, 30),
2488};
2489static const unsigned int msiof2_ss1_mux[] = {
2490	MSIOF2_SS1_MARK,
2491};
2492static const unsigned int msiof2_ss2_pins[] = {
2493	/* SS2 */
2494	RCAR_GP_PIN(0, 31),
2495};
2496static const unsigned int msiof2_ss2_mux[] = {
2497	MSIOF2_SS2_MARK,
2498};
2499static const unsigned int msiof2_rx_pins[] = {
2500	/* RXD */
2501	RCAR_GP_PIN(0, 29),
2502};
2503static const unsigned int msiof2_rx_mux[] = {
2504	MSIOF2_RXD_MARK,
2505};
2506static const unsigned int msiof2_tx_pins[] = {
2507	/* TXD */
2508	RCAR_GP_PIN(0, 28),
2509};
2510static const unsigned int msiof2_tx_mux[] = {
2511	MSIOF2_TXD_MARK,
2512};
2513/* - MSIOF3 ----------------------------------------------------------------- */
2514static const unsigned int msiof3_clk_pins[] = {
2515	/* SCK */
2516	RCAR_GP_PIN(5, 4),
2517};
2518static const unsigned int msiof3_clk_mux[] = {
2519	MSIOF3_SCK_MARK,
2520};
2521static const unsigned int msiof3_sync_pins[] = {
2522	/* SYNC */
2523	RCAR_GP_PIN(4, 30),
2524};
2525static const unsigned int msiof3_sync_mux[] = {
2526	MSIOF3_SYNC_MARK,
2527};
2528static const unsigned int msiof3_ss1_pins[] = {
2529	/* SS1 */
2530	RCAR_GP_PIN(4, 31),
2531};
2532static const unsigned int msiof3_ss1_mux[] = {
2533	MSIOF3_SS1_MARK,
2534};
2535static const unsigned int msiof3_ss2_pins[] = {
2536	/* SS2 */
2537	RCAR_GP_PIN(4, 27),
2538};
2539static const unsigned int msiof3_ss2_mux[] = {
2540	MSIOF3_SS2_MARK,
2541};
2542static const unsigned int msiof3_rx_pins[] = {
2543	/* RXD */
2544	RCAR_GP_PIN(5, 2),
2545};
2546static const unsigned int msiof3_rx_mux[] = {
2547	MSIOF3_RXD_MARK,
2548};
2549static const unsigned int msiof3_tx_pins[] = {
2550	/* TXD */
2551	RCAR_GP_PIN(5, 3),
2552};
2553static const unsigned int msiof3_tx_mux[] = {
2554	MSIOF3_TXD_MARK,
2555};
2556
2557static const unsigned int msiof3_clk_b_pins[] = {
2558	/* SCK */
2559	RCAR_GP_PIN(0, 0),
2560};
2561static const unsigned int msiof3_clk_b_mux[] = {
2562	MSIOF3_SCK_B_MARK,
2563};
2564static const unsigned int msiof3_sync_b_pins[] = {
2565	/* SYNC */
2566	RCAR_GP_PIN(0, 1),
2567};
2568static const unsigned int msiof3_sync_b_mux[] = {
2569	MSIOF3_SYNC_B_MARK,
2570};
2571static const unsigned int msiof3_rx_b_pins[] = {
2572	/* RXD */
2573	RCAR_GP_PIN(0, 2),
2574};
2575static const unsigned int msiof3_rx_b_mux[] = {
2576	MSIOF3_RXD_B_MARK,
2577};
2578static const unsigned int msiof3_tx_b_pins[] = {
2579	/* TXD */
2580	RCAR_GP_PIN(0, 3),
2581};
2582static const unsigned int msiof3_tx_b_mux[] = {
2583	MSIOF3_TXD_B_MARK,
2584};
2585/* - QSPI ------------------------------------------------------------------- */
2586static const unsigned int qspi_ctrl_pins[] = {
2587	/* SPCLK, SSL */
2588	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2589};
2590static const unsigned int qspi_ctrl_mux[] = {
2591	SPCLK_MARK, SSL_MARK,
2592};
2593static const unsigned int qspi_data2_pins[] = {
2594	/* MOSI_IO0, MISO_IO1 */
2595	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2596};
2597static const unsigned int qspi_data2_mux[] = {
2598	MOSI_IO0_MARK, MISO_IO1_MARK,
2599};
2600static const unsigned int qspi_data4_pins[] = {
2601	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2602	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2603	RCAR_GP_PIN(1, 8),
2604};
2605static const unsigned int qspi_data4_mux[] = {
2606	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2607};
2608/* - SCIF0 ------------------------------------------------------------------ */
2609static const unsigned int scif0_data_pins[] = {
2610	/* RX, TX */
2611	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2612};
2613static const unsigned int scif0_data_mux[] = {
2614	RX0_MARK, TX0_MARK,
2615};
2616static const unsigned int scif0_clk_pins[] = {
2617	/* SCK */
2618	RCAR_GP_PIN(4, 27),
2619};
2620static const unsigned int scif0_clk_mux[] = {
2621	SCK0_MARK,
2622};
2623static const unsigned int scif0_ctrl_pins[] = {
2624	/* RTS, CTS */
2625	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2626};
2627static const unsigned int scif0_ctrl_mux[] = {
2628	RTS0_N_MARK, CTS0_N_MARK,
2629};
2630static const unsigned int scif0_data_b_pins[] = {
2631	/* RX, TX */
2632	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2633};
2634static const unsigned int scif0_data_b_mux[] = {
2635	RX0_B_MARK, TX0_B_MARK,
2636};
2637/* - SCIF1 ------------------------------------------------------------------ */
2638static const unsigned int scif1_data_pins[] = {
2639	/* RX, TX */
2640	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2641};
2642static const unsigned int scif1_data_mux[] = {
2643	RX1_MARK, TX1_MARK,
2644};
2645static const unsigned int scif1_clk_pins[] = {
2646	/* SCK */
2647	RCAR_GP_PIN(4, 20),
2648};
2649static const unsigned int scif1_clk_mux[] = {
2650	SCK1_MARK,
2651};
2652static const unsigned int scif1_ctrl_pins[] = {
2653	/* RTS, CTS */
2654	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2655};
2656static const unsigned int scif1_ctrl_mux[] = {
2657	RTS1_N_MARK, CTS1_N_MARK,
2658};
2659static const unsigned int scif1_data_b_pins[] = {
2660	/* RX, TX */
2661	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2662};
2663static const unsigned int scif1_data_b_mux[] = {
2664	RX1_B_MARK, TX1_B_MARK,
2665};
2666static const unsigned int scif1_data_c_pins[] = {
2667	/* RX, TX */
2668	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2669};
2670static const unsigned int scif1_data_c_mux[] = {
2671	RX1_C_MARK, TX1_C_MARK,
2672};
2673static const unsigned int scif1_data_d_pins[] = {
2674	/* RX, TX */
2675	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2676};
2677static const unsigned int scif1_data_d_mux[] = {
2678	RX1_D_MARK, TX1_D_MARK,
2679};
2680static const unsigned int scif1_clk_d_pins[] = {
2681	/* SCK */
2682	RCAR_GP_PIN(3, 17),
2683};
2684static const unsigned int scif1_clk_d_mux[] = {
2685	SCK1_D_MARK,
2686};
2687static const unsigned int scif1_data_e_pins[] = {
2688	/* RX, TX */
2689	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2690};
2691static const unsigned int scif1_data_e_mux[] = {
2692	RX1_E_MARK, TX1_E_MARK,
2693};
2694static const unsigned int scif1_clk_e_pins[] = {
2695	/* SCK */
2696	RCAR_GP_PIN(2, 20),
2697};
2698static const unsigned int scif1_clk_e_mux[] = {
2699	SCK1_E_MARK,
2700};
2701/* - SCIF2 ------------------------------------------------------------------ */
2702static const unsigned int scif2_data_pins[] = {
2703	/* RX, TX */
2704	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2705};
2706static const unsigned int scif2_data_mux[] = {
2707	RX2_MARK, TX2_MARK,
2708};
2709static const unsigned int scif2_clk_pins[] = {
2710	/* SCK */
2711	RCAR_GP_PIN(5, 4),
2712};
2713static const unsigned int scif2_clk_mux[] = {
2714	SCK2_MARK,
2715};
2716static const unsigned int scif2_data_b_pins[] = {
2717	/* RX, TX */
2718	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2719};
2720static const unsigned int scif2_data_b_mux[] = {
2721	RX2_B_MARK, TX2_B_MARK,
2722};
2723/* - SCIFA0 ----------------------------------------------------------------- */
2724static const unsigned int scifa0_data_pins[] = {
2725	/* RXD, TXD */
2726	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2727};
2728static const unsigned int scifa0_data_mux[] = {
2729	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2730};
2731static const unsigned int scifa0_clk_pins[] = {
2732	/* SCK */
2733	RCAR_GP_PIN(4, 27),
2734};
2735static const unsigned int scifa0_clk_mux[] = {
2736	SCIFA0_SCK_MARK,
2737};
2738static const unsigned int scifa0_ctrl_pins[] = {
2739	/* RTS, CTS */
2740	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2741};
2742static const unsigned int scifa0_ctrl_mux[] = {
2743	SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2744};
2745static const unsigned int scifa0_data_b_pins[] = {
2746	/* RXD, TXD */
2747	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2748};
2749static const unsigned int scifa0_data_b_mux[] = {
2750	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2751};
2752static const unsigned int scifa0_clk_b_pins[] = {
2753	/* SCK */
2754	RCAR_GP_PIN(1, 19),
2755};
2756static const unsigned int scifa0_clk_b_mux[] = {
2757	SCIFA0_SCK_B_MARK,
2758};
2759static const unsigned int scifa0_ctrl_b_pins[] = {
2760	/* RTS, CTS */
2761	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2762};
2763static const unsigned int scifa0_ctrl_b_mux[] = {
2764	SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2765};
2766/* - SCIFA1 ----------------------------------------------------------------- */
2767static const unsigned int scifa1_data_pins[] = {
2768	/* RXD, TXD */
2769	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2770};
2771static const unsigned int scifa1_data_mux[] = {
2772	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2773};
2774static const unsigned int scifa1_clk_pins[] = {
2775	/* SCK */
2776	RCAR_GP_PIN(4, 20),
2777};
2778static const unsigned int scifa1_clk_mux[] = {
2779	SCIFA1_SCK_MARK,
2780};
2781static const unsigned int scifa1_ctrl_pins[] = {
2782	/* RTS, CTS */
2783	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2784};
2785static const unsigned int scifa1_ctrl_mux[] = {
2786	SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2787};
2788static const unsigned int scifa1_data_b_pins[] = {
2789	/* RXD, TXD */
2790	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2791};
2792static const unsigned int scifa1_data_b_mux[] = {
2793	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2794};
2795static const unsigned int scifa1_clk_b_pins[] = {
2796	/* SCK */
2797	RCAR_GP_PIN(0, 23),
2798};
2799static const unsigned int scifa1_clk_b_mux[] = {
2800	SCIFA1_SCK_B_MARK,
2801};
2802static const unsigned int scifa1_ctrl_b_pins[] = {
2803	/* RTS, CTS */
2804	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2805};
2806static const unsigned int scifa1_ctrl_b_mux[] = {
2807	SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2808};
2809static const unsigned int scifa1_data_c_pins[] = {
2810	/* RXD, TXD */
2811	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2812};
2813static const unsigned int scifa1_data_c_mux[] = {
2814	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2815};
2816static const unsigned int scifa1_clk_c_pins[] = {
2817	/* SCK */
2818	RCAR_GP_PIN(0, 8),
2819};
2820static const unsigned int scifa1_clk_c_mux[] = {
2821	SCIFA1_SCK_C_MARK,
2822};
2823static const unsigned int scifa1_ctrl_c_pins[] = {
2824	/* RTS, CTS */
2825	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2826};
2827static const unsigned int scifa1_ctrl_c_mux[] = {
2828	SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2829};
2830static const unsigned int scifa1_data_d_pins[] = {
2831	/* RXD, TXD */
2832	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2833};
2834static const unsigned int scifa1_data_d_mux[] = {
2835	SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2836};
2837static const unsigned int scifa1_clk_d_pins[] = {
2838	/* SCK */
2839	RCAR_GP_PIN(2, 10),
2840};
2841static const unsigned int scifa1_clk_d_mux[] = {
2842	SCIFA1_SCK_D_MARK,
2843};
2844static const unsigned int scifa1_ctrl_d_pins[] = {
2845	/* RTS, CTS */
2846	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2847};
2848static const unsigned int scifa1_ctrl_d_mux[] = {
2849	SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2850};
2851/* - SCIFA2 ----------------------------------------------------------------- */
2852static const unsigned int scifa2_data_pins[] = {
2853	/* RXD, TXD */
2854	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2855};
2856static const unsigned int scifa2_data_mux[] = {
2857	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2858};
2859static const unsigned int scifa2_clk_pins[] = {
2860	/* SCK */
2861	RCAR_GP_PIN(5, 4),
2862};
2863static const unsigned int scifa2_clk_mux[] = {
2864	SCIFA2_SCK_MARK,
2865};
2866static const unsigned int scifa2_ctrl_pins[] = {
2867	/* RTS, CTS */
2868	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2869};
2870static const unsigned int scifa2_ctrl_mux[] = {
2871	SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2872};
2873static const unsigned int scifa2_data_b_pins[] = {
2874	/* RXD, TXD */
2875	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2876};
2877static const unsigned int scifa2_data_b_mux[] = {
2878	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2879};
2880static const unsigned int scifa2_data_c_pins[] = {
2881	/* RXD, TXD */
2882	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2883};
2884static const unsigned int scifa2_data_c_mux[] = {
2885	SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2886};
2887static const unsigned int scifa2_clk_c_pins[] = {
2888	/* SCK */
2889	RCAR_GP_PIN(5, 29),
2890};
2891static const unsigned int scifa2_clk_c_mux[] = {
2892	SCIFA2_SCK_C_MARK,
2893};
2894/* - SCIFB0 ----------------------------------------------------------------- */
2895static const unsigned int scifb0_data_pins[] = {
2896	/* RXD, TXD */
2897	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2898};
2899static const unsigned int scifb0_data_mux[] = {
2900	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2901};
2902static const unsigned int scifb0_clk_pins[] = {
2903	/* SCK */
2904	RCAR_GP_PIN(4, 8),
2905};
2906static const unsigned int scifb0_clk_mux[] = {
2907	SCIFB0_SCK_MARK,
2908};
2909static const unsigned int scifb0_ctrl_pins[] = {
2910	/* RTS, CTS */
2911	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2912};
2913static const unsigned int scifb0_ctrl_mux[] = {
2914	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2915};
2916static const unsigned int scifb0_data_b_pins[] = {
2917	/* RXD, TXD */
2918	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2919};
2920static const unsigned int scifb0_data_b_mux[] = {
2921	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2922};
2923static const unsigned int scifb0_clk_b_pins[] = {
2924	/* SCK */
2925	RCAR_GP_PIN(3, 9),
2926};
2927static const unsigned int scifb0_clk_b_mux[] = {
2928	SCIFB0_SCK_B_MARK,
2929};
2930static const unsigned int scifb0_ctrl_b_pins[] = {
2931	/* RTS, CTS */
2932	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2933};
2934static const unsigned int scifb0_ctrl_b_mux[] = {
2935	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2936};
2937static const unsigned int scifb0_data_c_pins[] = {
2938	/* RXD, TXD */
2939	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2940};
2941static const unsigned int scifb0_data_c_mux[] = {
2942	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2943};
2944/* - SCIFB1 ----------------------------------------------------------------- */
2945static const unsigned int scifb1_data_pins[] = {
2946	/* RXD, TXD */
2947	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2948};
2949static const unsigned int scifb1_data_mux[] = {
2950	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2951};
2952static const unsigned int scifb1_clk_pins[] = {
2953	/* SCK */
2954	RCAR_GP_PIN(4, 14),
2955};
2956static const unsigned int scifb1_clk_mux[] = {
2957	SCIFB1_SCK_MARK,
2958};
2959static const unsigned int scifb1_ctrl_pins[] = {
2960	/* RTS, CTS */
2961	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2962};
2963static const unsigned int scifb1_ctrl_mux[] = {
2964	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2965};
2966static const unsigned int scifb1_data_b_pins[] = {
2967	/* RXD, TXD */
2968	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2969};
2970static const unsigned int scifb1_data_b_mux[] = {
2971	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2972};
2973static const unsigned int scifb1_clk_b_pins[] = {
2974	/* SCK */
2975	RCAR_GP_PIN(3, 1),
2976};
2977static const unsigned int scifb1_clk_b_mux[] = {
2978	SCIFB1_SCK_B_MARK,
2979};
2980static const unsigned int scifb1_ctrl_b_pins[] = {
2981	/* RTS, CTS */
2982	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2983};
2984static const unsigned int scifb1_ctrl_b_mux[] = {
2985	SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2986};
2987static const unsigned int scifb1_data_c_pins[] = {
2988	/* RXD, TXD */
2989	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2990};
2991static const unsigned int scifb1_data_c_mux[] = {
2992	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2993};
2994static const unsigned int scifb1_data_d_pins[] = {
2995	/* RXD, TXD */
2996	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2997};
2998static const unsigned int scifb1_data_d_mux[] = {
2999	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3000};
3001static const unsigned int scifb1_data_e_pins[] = {
3002	/* RXD, TXD */
3003	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3004};
3005static const unsigned int scifb1_data_e_mux[] = {
3006	SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3007};
3008static const unsigned int scifb1_clk_e_pins[] = {
3009	/* SCK */
3010	RCAR_GP_PIN(3, 17),
3011};
3012static const unsigned int scifb1_clk_e_mux[] = {
3013	SCIFB1_SCK_E_MARK,
3014};
3015static const unsigned int scifb1_data_f_pins[] = {
3016	/* RXD, TXD */
3017	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3018};
3019static const unsigned int scifb1_data_f_mux[] = {
3020	SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3021};
3022static const unsigned int scifb1_data_g_pins[] = {
3023	/* RXD, TXD */
3024	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3025};
3026static const unsigned int scifb1_data_g_mux[] = {
3027	SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3028};
3029static const unsigned int scifb1_clk_g_pins[] = {
3030	/* SCK */
3031	RCAR_GP_PIN(2, 20),
3032};
3033static const unsigned int scifb1_clk_g_mux[] = {
3034	SCIFB1_SCK_G_MARK,
3035};
3036/* - SCIFB2 ----------------------------------------------------------------- */
3037static const unsigned int scifb2_data_pins[] = {
3038	/* RXD, TXD */
3039	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3040};
3041static const unsigned int scifb2_data_mux[] = {
3042	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3043};
3044static const unsigned int scifb2_clk_pins[] = {
3045	/* SCK */
3046	RCAR_GP_PIN(4, 21),
3047};
3048static const unsigned int scifb2_clk_mux[] = {
3049	SCIFB2_SCK_MARK,
3050};
3051static const unsigned int scifb2_ctrl_pins[] = {
3052	/* RTS, CTS */
3053	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3054};
3055static const unsigned int scifb2_ctrl_mux[] = {
3056	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3057};
3058static const unsigned int scifb2_data_b_pins[] = {
3059	/* RXD, TXD */
3060	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3061};
3062static const unsigned int scifb2_data_b_mux[] = {
3063	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3064};
3065static const unsigned int scifb2_clk_b_pins[] = {
3066	/* SCK */
3067	RCAR_GP_PIN(0, 31),
3068};
3069static const unsigned int scifb2_clk_b_mux[] = {
3070	SCIFB2_SCK_B_MARK,
3071};
3072static const unsigned int scifb2_ctrl_b_pins[] = {
3073	/* RTS, CTS */
3074	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3075};
3076static const unsigned int scifb2_ctrl_b_mux[] = {
3077	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3078};
3079static const unsigned int scifb2_data_c_pins[] = {
3080	/* RXD, TXD */
3081	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3082};
3083static const unsigned int scifb2_data_c_mux[] = {
3084	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3085};
3086/* - SDHI0 ------------------------------------------------------------------ */
3087static const unsigned int sdhi0_data1_pins[] = {
3088	/* D0 */
3089	RCAR_GP_PIN(3, 2),
3090};
3091static const unsigned int sdhi0_data1_mux[] = {
3092	SD0_DAT0_MARK,
3093};
3094static const unsigned int sdhi0_data4_pins[] = {
3095	/* D[0:3] */
3096	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3097};
3098static const unsigned int sdhi0_data4_mux[] = {
3099	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3100};
3101static const unsigned int sdhi0_ctrl_pins[] = {
3102	/* CLK, CMD */
3103	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3104};
3105static const unsigned int sdhi0_ctrl_mux[] = {
3106	SD0_CLK_MARK, SD0_CMD_MARK,
3107};
3108static const unsigned int sdhi0_cd_pins[] = {
3109	/* CD */
3110	RCAR_GP_PIN(3, 6),
3111};
3112static const unsigned int sdhi0_cd_mux[] = {
3113	SD0_CD_MARK,
3114};
3115static const unsigned int sdhi0_wp_pins[] = {
3116	/* WP */
3117	RCAR_GP_PIN(3, 7),
3118};
3119static const unsigned int sdhi0_wp_mux[] = {
3120	SD0_WP_MARK,
3121};
3122/* - SDHI1 ------------------------------------------------------------------ */
3123static const unsigned int sdhi1_data1_pins[] = {
3124	/* D0 */
3125	RCAR_GP_PIN(3, 10),
3126};
3127static const unsigned int sdhi1_data1_mux[] = {
3128	SD1_DAT0_MARK,
3129};
3130static const unsigned int sdhi1_data4_pins[] = {
3131	/* D[0:3] */
3132	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3133};
3134static const unsigned int sdhi1_data4_mux[] = {
3135	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3136};
3137static const unsigned int sdhi1_ctrl_pins[] = {
3138	/* CLK, CMD */
3139	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3140};
3141static const unsigned int sdhi1_ctrl_mux[] = {
3142	SD1_CLK_MARK, SD1_CMD_MARK,
3143};
3144static const unsigned int sdhi1_cd_pins[] = {
3145	/* CD */
3146	RCAR_GP_PIN(3, 14),
3147};
3148static const unsigned int sdhi1_cd_mux[] = {
3149	SD1_CD_MARK,
3150};
3151static const unsigned int sdhi1_wp_pins[] = {
3152	/* WP */
3153	RCAR_GP_PIN(3, 15),
3154};
3155static const unsigned int sdhi1_wp_mux[] = {
3156	SD1_WP_MARK,
3157};
3158/* - SDHI2 ------------------------------------------------------------------ */
3159static const unsigned int sdhi2_data1_pins[] = {
3160	/* D0 */
3161	RCAR_GP_PIN(3, 18),
3162};
3163static const unsigned int sdhi2_data1_mux[] = {
3164	SD2_DAT0_MARK,
3165};
3166static const unsigned int sdhi2_data4_pins[] = {
3167	/* D[0:3] */
3168	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3169};
3170static const unsigned int sdhi2_data4_mux[] = {
3171	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3172};
3173static const unsigned int sdhi2_ctrl_pins[] = {
3174	/* CLK, CMD */
3175	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3176};
3177static const unsigned int sdhi2_ctrl_mux[] = {
3178	SD2_CLK_MARK, SD2_CMD_MARK,
3179};
3180static const unsigned int sdhi2_cd_pins[] = {
3181	/* CD */
3182	RCAR_GP_PIN(3, 22),
3183};
3184static const unsigned int sdhi2_cd_mux[] = {
3185	SD2_CD_MARK,
3186};
3187static const unsigned int sdhi2_wp_pins[] = {
3188	/* WP */
3189	RCAR_GP_PIN(3, 23),
3190};
3191static const unsigned int sdhi2_wp_mux[] = {
3192	SD2_WP_MARK,
3193};
3194/* - SDHI3 ------------------------------------------------------------------ */
3195static const unsigned int sdhi3_data1_pins[] = {
3196	/* D0 */
3197	RCAR_GP_PIN(3, 26),
3198};
3199static const unsigned int sdhi3_data1_mux[] = {
3200	SD3_DAT0_MARK,
3201};
3202static const unsigned int sdhi3_data4_pins[] = {
3203	/* D[0:3] */
3204	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3205};
3206static const unsigned int sdhi3_data4_mux[] = {
3207	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3208};
3209static const unsigned int sdhi3_ctrl_pins[] = {
3210	/* CLK, CMD */
3211	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3212};
3213static const unsigned int sdhi3_ctrl_mux[] = {
3214	SD3_CLK_MARK, SD3_CMD_MARK,
3215};
3216static const unsigned int sdhi3_cd_pins[] = {
3217	/* CD */
3218	RCAR_GP_PIN(3, 30),
3219};
3220static const unsigned int sdhi3_cd_mux[] = {
3221	SD3_CD_MARK,
3222};
3223static const unsigned int sdhi3_wp_pins[] = {
3224	/* WP */
3225	RCAR_GP_PIN(3, 31),
3226};
3227static const unsigned int sdhi3_wp_mux[] = {
3228	SD3_WP_MARK,
3229};
3230/* - SSI -------------------------------------------------------------------- */
3231static const unsigned int ssi0_data_pins[] = {
3232	/* SDATA0 */
3233	RCAR_GP_PIN(4, 5),
3234};
3235static const unsigned int ssi0_data_mux[] = {
3236	SSI_SDATA0_MARK,
3237};
3238static const unsigned int ssi0129_ctrl_pins[] = {
3239	/* SCK, WS */
3240	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3241};
3242static const unsigned int ssi0129_ctrl_mux[] = {
3243	SSI_SCK0129_MARK, SSI_WS0129_MARK,
3244};
3245static const unsigned int ssi1_data_pins[] = {
3246	/* SDATA1 */
3247	RCAR_GP_PIN(4, 6),
3248};
3249static const unsigned int ssi1_data_mux[] = {
3250	SSI_SDATA1_MARK,
3251};
3252static const unsigned int ssi1_ctrl_pins[] = {
3253	/* SCK, WS */
3254	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3255};
3256static const unsigned int ssi1_ctrl_mux[] = {
3257	SSI_SCK1_MARK, SSI_WS1_MARK,
3258};
3259static const unsigned int ssi2_data_pins[] = {
3260	/* SDATA2 */
3261	RCAR_GP_PIN(4, 7),
3262};
3263static const unsigned int ssi2_data_mux[] = {
3264	SSI_SDATA2_MARK,
3265};
3266static const unsigned int ssi2_ctrl_pins[] = {
3267	/* SCK, WS */
3268	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3269};
3270static const unsigned int ssi2_ctrl_mux[] = {
3271	SSI_SCK2_MARK, SSI_WS2_MARK,
3272};
3273static const unsigned int ssi3_data_pins[] = {
3274	/* SDATA3 */
3275	RCAR_GP_PIN(4, 10),
3276};
3277static const unsigned int ssi3_data_mux[] = {
3278	SSI_SDATA3_MARK
3279};
3280static const unsigned int ssi34_ctrl_pins[] = {
3281	/* SCK, WS */
3282	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3283};
3284static const unsigned int ssi34_ctrl_mux[] = {
3285	SSI_SCK34_MARK, SSI_WS34_MARK,
3286};
3287static const unsigned int ssi4_data_pins[] = {
3288	/* SDATA4 */
3289	RCAR_GP_PIN(4, 13),
3290};
3291static const unsigned int ssi4_data_mux[] = {
3292	SSI_SDATA4_MARK,
3293};
3294static const unsigned int ssi4_ctrl_pins[] = {
3295	/* SCK, WS */
3296	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3297};
3298static const unsigned int ssi4_ctrl_mux[] = {
3299	SSI_SCK4_MARK, SSI_WS4_MARK,
3300};
3301static const unsigned int ssi5_pins[] = {
3302	/* SDATA5, SCK, WS */
3303	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3304};
3305static const unsigned int ssi5_mux[] = {
3306	SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3307};
3308static const unsigned int ssi5_b_pins[] = {
3309	/* SDATA5, SCK, WS */
3310	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3311};
3312static const unsigned int ssi5_b_mux[] = {
3313	SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3314};
3315static const unsigned int ssi5_c_pins[] = {
3316	/* SDATA5, SCK, WS */
3317	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3318};
3319static const unsigned int ssi5_c_mux[] = {
3320	SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3321};
3322static const unsigned int ssi6_pins[] = {
3323	/* SDATA6, SCK, WS */
3324	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3325};
3326static const unsigned int ssi6_mux[] = {
3327	SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3328};
3329static const unsigned int ssi6_b_pins[] = {
3330	/* SDATA6, SCK, WS */
3331	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3332};
3333static const unsigned int ssi6_b_mux[] = {
3334	SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3335};
3336static const unsigned int ssi7_data_pins[] = {
3337	/* SDATA7 */
3338	RCAR_GP_PIN(4, 22),
3339};
3340static const unsigned int ssi7_data_mux[] = {
3341	SSI_SDATA7_MARK,
3342};
3343static const unsigned int ssi7_b_data_pins[] = {
3344	/* SDATA7 */
3345	RCAR_GP_PIN(4, 22),
3346};
3347static const unsigned int ssi7_b_data_mux[] = {
3348	SSI_SDATA7_B_MARK,
3349};
3350static const unsigned int ssi7_c_data_pins[] = {
3351	/* SDATA7 */
3352	RCAR_GP_PIN(1, 26),
3353};
3354static const unsigned int ssi7_c_data_mux[] = {
3355	SSI_SDATA7_C_MARK,
3356};
3357static const unsigned int ssi78_ctrl_pins[] = {
3358	/* SCK, WS */
3359	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3360};
3361static const unsigned int ssi78_ctrl_mux[] = {
3362	SSI_SCK78_MARK, SSI_WS78_MARK,
3363};
3364static const unsigned int ssi78_b_ctrl_pins[] = {
3365	/* SCK, WS */
3366	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3367};
3368static const unsigned int ssi78_b_ctrl_mux[] = {
3369	SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3370};
3371static const unsigned int ssi78_c_ctrl_pins[] = {
3372	/* SCK, WS */
3373	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3374};
3375static const unsigned int ssi78_c_ctrl_mux[] = {
3376	SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3377};
3378static const unsigned int ssi8_data_pins[] = {
3379	/* SDATA8 */
3380	RCAR_GP_PIN(4, 23),
3381};
3382static const unsigned int ssi8_data_mux[] = {
3383	SSI_SDATA8_MARK,
3384};
3385static const unsigned int ssi8_b_data_pins[] = {
3386	/* SDATA8 */
3387	RCAR_GP_PIN(4, 23),
3388};
3389static const unsigned int ssi8_b_data_mux[] = {
3390	SSI_SDATA8_B_MARK,
3391};
3392static const unsigned int ssi8_c_data_pins[] = {
3393	/* SDATA8 */
3394	RCAR_GP_PIN(1, 27),
3395};
3396static const unsigned int ssi8_c_data_mux[] = {
3397	SSI_SDATA8_C_MARK,
3398};
3399static const unsigned int ssi9_data_pins[] = {
3400	/* SDATA9 */
3401	RCAR_GP_PIN(4, 24),
3402};
3403static const unsigned int ssi9_data_mux[] = {
3404	SSI_SDATA9_MARK,
3405};
3406static const unsigned int ssi9_ctrl_pins[] = {
3407	/* SCK, WS */
3408	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3409};
3410static const unsigned int ssi9_ctrl_mux[] = {
3411	SSI_SCK9_MARK, SSI_WS9_MARK,
3412};
3413/* - TPU0 ------------------------------------------------------------------- */
3414static const unsigned int tpu0_to0_pins[] = {
3415	/* TO */
3416	RCAR_GP_PIN(0, 20),
3417};
3418static const unsigned int tpu0_to0_mux[] = {
3419	TPU0TO0_MARK,
3420};
3421static const unsigned int tpu0_to1_pins[] = {
3422	/* TO */
3423	RCAR_GP_PIN(0, 21),
3424};
3425static const unsigned int tpu0_to1_mux[] = {
3426	TPU0TO1_MARK,
3427};
3428static const unsigned int tpu0_to2_pins[] = {
3429	/* TO */
3430	RCAR_GP_PIN(0, 22),
3431};
3432static const unsigned int tpu0_to2_mux[] = {
3433	TPU0TO2_MARK,
3434};
3435static const unsigned int tpu0_to3_pins[] = {
3436	/* TO */
3437	RCAR_GP_PIN(0, 23),
3438};
3439static const unsigned int tpu0_to3_mux[] = {
3440	TPU0TO3_MARK,
3441};
3442/* - USB0 ------------------------------------------------------------------- */
3443static const unsigned int usb0_pins[] = {
3444	/* PWEN, OVC/VBUS */
3445	RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3446};
3447static const unsigned int usb0_mux[] = {
3448	USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3449};
3450static const unsigned int usb0_ovc_vbus_pins[] = {
3451	/* OVC/VBUS */
3452	RCAR_GP_PIN(5, 19),
3453};
3454static const unsigned int usb0_ovc_vbus_mux[] = {
3455	USB0_OVC_VBUS_MARK,
3456};
3457/* - USB1 ------------------------------------------------------------------- */
3458static const unsigned int usb1_pins[] = {
3459	/* PWEN, OVC */
3460	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3461};
3462static const unsigned int usb1_mux[] = {
3463	USB1_PWEN_MARK, USB1_OVC_MARK,
3464};
3465/* - USB2 ------------------------------------------------------------------- */
3466static const unsigned int usb2_pins[] = {
3467	/* PWEN, OVC */
3468	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3469};
3470static const unsigned int usb2_mux[] = {
3471	USB2_PWEN_MARK, USB2_OVC_MARK,
3472};
3473
3474union vin_data {
3475	unsigned int data24[24];
3476	unsigned int data20[20];
3477	unsigned int data16[16];
3478	unsigned int data12[12];
3479	unsigned int data10[10];
3480	unsigned int data8[8];
3481	unsigned int data4[4];
3482};
3483
3484#define VIN_DATA_PIN_GROUP(n, s)				\
3485	{							\
3486		.name = #n#s,					\
3487		.pins = n##_pins.data##s,			\
3488		.mux = n##_mux.data##s,				\
3489		.nr_pins = ARRAY_SIZE(n##_pins.data##s),	\
3490	}
3491
3492/* - VIN0 ------------------------------------------------------------------- */
3493static const union vin_data vin0_data_pins = {
3494	.data24 = {
3495		/* B */
3496		RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3497		RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3498		RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3499		RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3500		/* G */
3501		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3502		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3503		RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3504		RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3505		/* R */
3506		RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3507		RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3508		RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3509		RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3510	},
3511};
3512static const union vin_data vin0_data_mux = {
3513	.data24 = {
3514		/* B */
3515		VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3516		VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3517		VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3518		VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3519		/* G */
3520		VI0_G0_MARK, VI0_G1_MARK,
3521		VI0_G2_MARK, VI0_G3_MARK,
3522		VI0_G4_MARK, VI0_G5_MARK,
3523		VI0_G6_MARK, VI0_G7_MARK,
3524		/* R */
3525		VI0_R0_MARK, VI0_R1_MARK,
3526		VI0_R2_MARK, VI0_R3_MARK,
3527		VI0_R4_MARK, VI0_R5_MARK,
3528		VI0_R6_MARK, VI0_R7_MARK,
3529	},
3530};
3531static const unsigned int vin0_data18_pins[] = {
3532	/* B */
3533	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3534	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3535	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3536	/* G */
3537	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3538	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3539	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3540	/* R */
3541	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3542	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3543	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3544};
3545static const unsigned int vin0_data18_mux[] = {
3546	/* B */
3547	VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3548	VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3549	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3550	/* G */
3551	VI0_G2_MARK, VI0_G3_MARK,
3552	VI0_G4_MARK, VI0_G5_MARK,
3553	VI0_G6_MARK, VI0_G7_MARK,
3554	/* R */
3555	VI0_R2_MARK, VI0_R3_MARK,
3556	VI0_R4_MARK, VI0_R5_MARK,
3557	VI0_R6_MARK, VI0_R7_MARK,
3558};
3559static const unsigned int vin0_sync_pins[] = {
3560	RCAR_GP_PIN(0, 12), /* HSYNC */
3561	RCAR_GP_PIN(0, 13), /* VSYNC */
3562};
3563static const unsigned int vin0_sync_mux[] = {
3564	VI0_HSYNC_N_MARK,
3565	VI0_VSYNC_N_MARK,
3566};
3567static const unsigned int vin0_field_pins[] = {
3568	RCAR_GP_PIN(0, 15),
3569};
3570static const unsigned int vin0_field_mux[] = {
3571	VI0_FIELD_MARK,
3572};
3573static const unsigned int vin0_clkenb_pins[] = {
3574	RCAR_GP_PIN(0, 14),
3575};
3576static const unsigned int vin0_clkenb_mux[] = {
3577	VI0_CLKENB_MARK,
3578};
3579static const unsigned int vin0_clk_pins[] = {
3580	RCAR_GP_PIN(2, 0),
3581};
3582static const unsigned int vin0_clk_mux[] = {
3583	VI0_CLK_MARK,
3584};
3585/* - VIN1 ------------------------------------------------------------------- */
3586static const union vin_data vin1_data_pins = {
3587	.data24 = {
3588		/* B */
3589		RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3590		RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3591		RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3592		RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3593		/* G */
3594		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3595		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3596		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3597		RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3598		/* R */
3599		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3600		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3601		RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3602		RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3603	},
3604};
3605static const union vin_data vin1_data_mux = {
3606	.data24 = {
3607		/* B */
3608		VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3609		VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3610		VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3611		VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3612		/* G */
3613		VI1_G0_MARK, VI1_G1_MARK,
3614		VI1_G2_MARK, VI1_G3_MARK,
3615		VI1_G4_MARK, VI1_G5_MARK,
3616		VI1_G6_MARK, VI1_G7_MARK,
3617		/* R */
3618		VI1_R0_MARK, VI1_R1_MARK,
3619		VI1_R2_MARK, VI1_R3_MARK,
3620		VI1_R4_MARK, VI1_R5_MARK,
3621		VI1_R6_MARK, VI1_R7_MARK,
3622	},
3623};
3624static const unsigned int vin1_data18_pins[] = {
3625	/* B */
3626	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3627	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3628	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3629	/* G */
3630	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3631	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3632	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3633	/* R */
3634	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3635	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3636	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3637};
3638static const unsigned int vin1_data18_mux[] = {
3639	/* B */
3640	VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3641	VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3642	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3643	/* G */
3644	VI1_G2_MARK, VI1_G3_MARK,
3645	VI1_G4_MARK, VI1_G5_MARK,
3646	VI1_G6_MARK, VI1_G7_MARK,
3647	/* R */
3648	VI1_R2_MARK, VI1_R3_MARK,
3649	VI1_R4_MARK, VI1_R5_MARK,
3650	VI1_R6_MARK, VI1_R7_MARK,
3651};
3652static const unsigned int vin1_sync_pins[] = {
3653	RCAR_GP_PIN(1, 24), /* HSYNC */
3654	RCAR_GP_PIN(1, 25), /* VSYNC */
3655};
3656static const unsigned int vin1_sync_mux[] = {
3657	VI1_HSYNC_N_MARK,
3658	VI1_VSYNC_N_MARK,
3659};
3660static const unsigned int vin1_field_pins[] = {
3661	RCAR_GP_PIN(1, 13),
3662};
3663static const unsigned int vin1_field_mux[] = {
3664	VI1_FIELD_MARK,
3665};
3666static const unsigned int vin1_clkenb_pins[] = {
3667	RCAR_GP_PIN(1, 26),
3668};
3669static const unsigned int vin1_clkenb_mux[] = {
3670	VI1_CLKENB_MARK,
3671};
3672static const unsigned int vin1_clk_pins[] = {
3673	RCAR_GP_PIN(2, 9),
3674};
3675static const unsigned int vin1_clk_mux[] = {
3676	VI1_CLK_MARK,
3677};
3678/* - VIN2 ----------------------------------------------------------------- */
3679static const union vin_data vin2_data_pins = {
3680	.data24 = {
3681		/* B */
3682		RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3683		RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3684		RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3685		RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3686		/* G */
3687		RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3688		RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3689		RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3690		RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3691		/* R */
3692		RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3693		RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3694		RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3695		RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3696	},
3697};
3698static const union vin_data vin2_data_mux = {
3699	.data24 = {
3700		/* B */
3701		VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3702		VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3703		VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3704		VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3705		/* G */
3706		VI2_G0_MARK, VI2_G1_MARK,
3707		VI2_G2_MARK, VI2_G3_MARK,
3708		VI2_G4_MARK, VI2_G5_MARK,
3709		VI2_G6_MARK, VI2_G7_MARK,
3710		/* R */
3711		VI2_R0_MARK, VI2_R1_MARK,
3712		VI2_R2_MARK, VI2_R3_MARK,
3713		VI2_R4_MARK, VI2_R5_MARK,
3714		VI2_R6_MARK, VI2_R7_MARK,
3715	},
3716};
3717static const unsigned int vin2_data18_pins[] = {
3718	/* B */
3719	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3720	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3721	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3722	/* G */
3723	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3724	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3725	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3726	/* R */
3727	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3728	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3729	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3730};
3731static const unsigned int vin2_data18_mux[] = {
3732	/* B */
3733	VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3734	VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3735	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3736	/* G */
3737	VI2_G2_MARK, VI2_G3_MARK,
3738	VI2_G4_MARK, VI2_G5_MARK,
3739	VI2_G6_MARK, VI2_G7_MARK,
3740	/* R */
3741	VI2_R2_MARK, VI2_R3_MARK,
3742	VI2_R4_MARK, VI2_R5_MARK,
3743	VI2_R6_MARK, VI2_R7_MARK,
3744};
3745static const unsigned int vin2_sync_pins[] = {
3746	RCAR_GP_PIN(1, 16), /* HSYNC */
3747	RCAR_GP_PIN(1, 21), /* VSYNC */
3748};
3749static const unsigned int vin2_sync_mux[] = {
3750	VI2_HSYNC_N_MARK,
3751	VI2_VSYNC_N_MARK,
3752};
3753static const unsigned int vin2_field_pins[] = {
3754	RCAR_GP_PIN(1, 9),
3755};
3756static const unsigned int vin2_field_mux[] = {
3757	VI2_FIELD_MARK,
3758};
3759static const unsigned int vin2_clkenb_pins[] = {
3760	RCAR_GP_PIN(1, 8),
3761};
3762static const unsigned int vin2_clkenb_mux[] = {
3763	VI2_CLKENB_MARK,
3764};
3765static const unsigned int vin2_clk_pins[] = {
3766	RCAR_GP_PIN(1, 11),
3767};
3768static const unsigned int vin2_clk_mux[] = {
3769	VI2_CLK_MARK,
3770};
3771/* - VIN3 ----------------------------------------------------------------- */
3772static const unsigned int vin3_data8_pins[] = {
3773	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3774	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3775	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3776	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3777};
3778static const unsigned int vin3_data8_mux[] = {
3779	VI3_DATA0_MARK, VI3_DATA1_MARK,
3780	VI3_DATA2_MARK, VI3_DATA3_MARK,
3781	VI3_DATA4_MARK, VI3_DATA5_MARK,
3782	VI3_DATA6_MARK, VI3_DATA7_MARK,
3783};
3784static const unsigned int vin3_sync_pins[] = {
3785	RCAR_GP_PIN(1, 16), /* HSYNC */
3786	RCAR_GP_PIN(1, 17), /* VSYNC */
3787};
3788static const unsigned int vin3_sync_mux[] = {
3789	VI3_HSYNC_N_MARK,
3790	VI3_VSYNC_N_MARK,
3791};
3792static const unsigned int vin3_field_pins[] = {
3793	RCAR_GP_PIN(1, 15),
3794};
3795static const unsigned int vin3_field_mux[] = {
3796	VI3_FIELD_MARK,
3797};
3798static const unsigned int vin3_clkenb_pins[] = {
3799	RCAR_GP_PIN(1, 14),
3800};
3801static const unsigned int vin3_clkenb_mux[] = {
3802	VI3_CLKENB_MARK,
3803};
3804static const unsigned int vin3_clk_pins[] = {
3805	RCAR_GP_PIN(1, 23),
3806};
3807static const unsigned int vin3_clk_mux[] = {
3808	VI3_CLK_MARK,
3809};
3810
3811static const struct sh_pfc_pin_group pinmux_groups[] = {
3812	SH_PFC_PIN_GROUP(audio_clk_a),
3813	SH_PFC_PIN_GROUP(audio_clk_b),
3814	SH_PFC_PIN_GROUP(audio_clk_c),
3815	SH_PFC_PIN_GROUP(audio_clkout),
3816	SH_PFC_PIN_GROUP(audio_clkout_b),
3817	SH_PFC_PIN_GROUP(audio_clkout_c),
3818	SH_PFC_PIN_GROUP(audio_clkout_d),
3819	SH_PFC_PIN_GROUP(du_rgb666),
3820	SH_PFC_PIN_GROUP(du_rgb888),
3821	SH_PFC_PIN_GROUP(du_clk_out_0),
3822	SH_PFC_PIN_GROUP(du_clk_out_1),
3823	SH_PFC_PIN_GROUP(du_sync_0),
3824	SH_PFC_PIN_GROUP(du_sync_1),
3825	SH_PFC_PIN_GROUP(du_cde),
3826	SH_PFC_PIN_GROUP(du0_clk_in),
3827	SH_PFC_PIN_GROUP(du1_clk_in),
3828	SH_PFC_PIN_GROUP(du2_clk_in),
3829	SH_PFC_PIN_GROUP(eth_link),
3830	SH_PFC_PIN_GROUP(eth_magic),
3831	SH_PFC_PIN_GROUP(eth_mdio),
3832	SH_PFC_PIN_GROUP(eth_rmii),
3833	SH_PFC_PIN_GROUP(hscif0_data),
3834	SH_PFC_PIN_GROUP(hscif0_clk),
3835	SH_PFC_PIN_GROUP(hscif0_ctrl),
3836	SH_PFC_PIN_GROUP(hscif0_data_b),
3837	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3838	SH_PFC_PIN_GROUP(hscif0_data_c),
3839	SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3840	SH_PFC_PIN_GROUP(hscif0_data_d),
3841	SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3842	SH_PFC_PIN_GROUP(hscif0_data_e),
3843	SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3844	SH_PFC_PIN_GROUP(hscif0_data_f),
3845	SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3846	SH_PFC_PIN_GROUP(hscif1_data),
3847	SH_PFC_PIN_GROUP(hscif1_clk),
3848	SH_PFC_PIN_GROUP(hscif1_ctrl),
3849	SH_PFC_PIN_GROUP(hscif1_data_b),
3850	SH_PFC_PIN_GROUP(hscif1_clk_b),
3851	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3852	SH_PFC_PIN_GROUP(i2c0),
3853	SH_PFC_PIN_GROUP(i2c1),
3854	SH_PFC_PIN_GROUP(i2c1_b),
3855	SH_PFC_PIN_GROUP(i2c1_c),
3856	SH_PFC_PIN_GROUP(i2c2),
3857	SH_PFC_PIN_GROUP(i2c2_b),
3858	SH_PFC_PIN_GROUP(i2c2_c),
3859	SH_PFC_PIN_GROUP(i2c2_d),
3860	SH_PFC_PIN_GROUP(i2c2_e),
3861	SH_PFC_PIN_GROUP(i2c3),
3862	SH_PFC_PIN_GROUP(iic0),
3863	SH_PFC_PIN_GROUP(iic1),
3864	SH_PFC_PIN_GROUP(iic1_b),
3865	SH_PFC_PIN_GROUP(iic1_c),
3866	SH_PFC_PIN_GROUP(iic2),
3867	SH_PFC_PIN_GROUP(iic2_b),
3868	SH_PFC_PIN_GROUP(iic2_c),
3869	SH_PFC_PIN_GROUP(iic2_d),
3870	SH_PFC_PIN_GROUP(iic2_e),
3871	SH_PFC_PIN_GROUP(iic3),
3872	SH_PFC_PIN_GROUP(intc_irq0),
3873	SH_PFC_PIN_GROUP(intc_irq1),
3874	SH_PFC_PIN_GROUP(intc_irq2),
3875	SH_PFC_PIN_GROUP(intc_irq3),
3876	SH_PFC_PIN_GROUP(mmc0_data1),
3877	SH_PFC_PIN_GROUP(mmc0_data4),
3878	SH_PFC_PIN_GROUP(mmc0_data8),
3879	SH_PFC_PIN_GROUP(mmc0_ctrl),
3880	SH_PFC_PIN_GROUP(mmc1_data1),
3881	SH_PFC_PIN_GROUP(mmc1_data4),
3882	SH_PFC_PIN_GROUP(mmc1_data8),
3883	SH_PFC_PIN_GROUP(mmc1_ctrl),
3884	SH_PFC_PIN_GROUP(msiof0_clk),
3885	SH_PFC_PIN_GROUP(msiof0_sync),
3886	SH_PFC_PIN_GROUP(msiof0_ss1),
3887	SH_PFC_PIN_GROUP(msiof0_ss2),
3888	SH_PFC_PIN_GROUP(msiof0_rx),
3889	SH_PFC_PIN_GROUP(msiof0_tx),
3890	SH_PFC_PIN_GROUP(msiof0_clk_b),
3891	SH_PFC_PIN_GROUP(msiof0_ss1_b),
3892	SH_PFC_PIN_GROUP(msiof0_ss2_b),
3893	SH_PFC_PIN_GROUP(msiof0_rx_b),
3894	SH_PFC_PIN_GROUP(msiof0_tx_b),
3895	SH_PFC_PIN_GROUP(msiof1_clk),
3896	SH_PFC_PIN_GROUP(msiof1_sync),
3897	SH_PFC_PIN_GROUP(msiof1_ss1),
3898	SH_PFC_PIN_GROUP(msiof1_ss2),
3899	SH_PFC_PIN_GROUP(msiof1_rx),
3900	SH_PFC_PIN_GROUP(msiof1_tx),
3901	SH_PFC_PIN_GROUP(msiof1_clk_b),
3902	SH_PFC_PIN_GROUP(msiof1_ss1_b),
3903	SH_PFC_PIN_GROUP(msiof1_ss2_b),
3904	SH_PFC_PIN_GROUP(msiof1_rx_b),
3905	SH_PFC_PIN_GROUP(msiof1_tx_b),
3906	SH_PFC_PIN_GROUP(msiof2_clk),
3907	SH_PFC_PIN_GROUP(msiof2_sync),
3908	SH_PFC_PIN_GROUP(msiof2_ss1),
3909	SH_PFC_PIN_GROUP(msiof2_ss2),
3910	SH_PFC_PIN_GROUP(msiof2_rx),
3911	SH_PFC_PIN_GROUP(msiof2_tx),
3912	SH_PFC_PIN_GROUP(msiof3_clk),
3913	SH_PFC_PIN_GROUP(msiof3_sync),
3914	SH_PFC_PIN_GROUP(msiof3_ss1),
3915	SH_PFC_PIN_GROUP(msiof3_ss2),
3916	SH_PFC_PIN_GROUP(msiof3_rx),
3917	SH_PFC_PIN_GROUP(msiof3_tx),
3918	SH_PFC_PIN_GROUP(msiof3_clk_b),
3919	SH_PFC_PIN_GROUP(msiof3_sync_b),
3920	SH_PFC_PIN_GROUP(msiof3_rx_b),
3921	SH_PFC_PIN_GROUP(msiof3_tx_b),
3922	SH_PFC_PIN_GROUP(qspi_ctrl),
3923	SH_PFC_PIN_GROUP(qspi_data2),
3924	SH_PFC_PIN_GROUP(qspi_data4),
3925	SH_PFC_PIN_GROUP(scif0_data),
3926	SH_PFC_PIN_GROUP(scif0_clk),
3927	SH_PFC_PIN_GROUP(scif0_ctrl),
3928	SH_PFC_PIN_GROUP(scif0_data_b),
3929	SH_PFC_PIN_GROUP(scif1_data),
3930	SH_PFC_PIN_GROUP(scif1_clk),
3931	SH_PFC_PIN_GROUP(scif1_ctrl),
3932	SH_PFC_PIN_GROUP(scif1_data_b),
3933	SH_PFC_PIN_GROUP(scif1_data_c),
3934	SH_PFC_PIN_GROUP(scif1_data_d),
3935	SH_PFC_PIN_GROUP(scif1_clk_d),
3936	SH_PFC_PIN_GROUP(scif1_data_e),
3937	SH_PFC_PIN_GROUP(scif1_clk_e),
3938	SH_PFC_PIN_GROUP(scif2_data),
3939	SH_PFC_PIN_GROUP(scif2_clk),
3940	SH_PFC_PIN_GROUP(scif2_data_b),
3941	SH_PFC_PIN_GROUP(scifa0_data),
3942	SH_PFC_PIN_GROUP(scifa0_clk),
3943	SH_PFC_PIN_GROUP(scifa0_ctrl),
3944	SH_PFC_PIN_GROUP(scifa0_data_b),
3945	SH_PFC_PIN_GROUP(scifa0_clk_b),
3946	SH_PFC_PIN_GROUP(scifa0_ctrl_b),
3947	SH_PFC_PIN_GROUP(scifa1_data),
3948	SH_PFC_PIN_GROUP(scifa1_clk),
3949	SH_PFC_PIN_GROUP(scifa1_ctrl),
3950	SH_PFC_PIN_GROUP(scifa1_data_b),
3951	SH_PFC_PIN_GROUP(scifa1_clk_b),
3952	SH_PFC_PIN_GROUP(scifa1_ctrl_b),
3953	SH_PFC_PIN_GROUP(scifa1_data_c),
3954	SH_PFC_PIN_GROUP(scifa1_clk_c),
3955	SH_PFC_PIN_GROUP(scifa1_ctrl_c),
3956	SH_PFC_PIN_GROUP(scifa1_data_d),
3957	SH_PFC_PIN_GROUP(scifa1_clk_d),
3958	SH_PFC_PIN_GROUP(scifa1_ctrl_d),
3959	SH_PFC_PIN_GROUP(scifa2_data),
3960	SH_PFC_PIN_GROUP(scifa2_clk),
3961	SH_PFC_PIN_GROUP(scifa2_ctrl),
3962	SH_PFC_PIN_GROUP(scifa2_data_b),
3963	SH_PFC_PIN_GROUP(scifa2_data_c),
3964	SH_PFC_PIN_GROUP(scifa2_clk_c),
3965	SH_PFC_PIN_GROUP(scifb0_data),
3966	SH_PFC_PIN_GROUP(scifb0_clk),
3967	SH_PFC_PIN_GROUP(scifb0_ctrl),
3968	SH_PFC_PIN_GROUP(scifb0_data_b),
3969	SH_PFC_PIN_GROUP(scifb0_clk_b),
3970	SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3971	SH_PFC_PIN_GROUP(scifb0_data_c),
3972	SH_PFC_PIN_GROUP(scifb1_data),
3973	SH_PFC_PIN_GROUP(scifb1_clk),
3974	SH_PFC_PIN_GROUP(scifb1_ctrl),
3975	SH_PFC_PIN_GROUP(scifb1_data_b),
3976	SH_PFC_PIN_GROUP(scifb1_clk_b),
3977	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
3978	SH_PFC_PIN_GROUP(scifb1_data_c),
3979	SH_PFC_PIN_GROUP(scifb1_data_d),
3980	SH_PFC_PIN_GROUP(scifb1_data_e),
3981	SH_PFC_PIN_GROUP(scifb1_clk_e),
3982	SH_PFC_PIN_GROUP(scifb1_data_f),
3983	SH_PFC_PIN_GROUP(scifb1_data_g),
3984	SH_PFC_PIN_GROUP(scifb1_clk_g),
3985	SH_PFC_PIN_GROUP(scifb2_data),
3986	SH_PFC_PIN_GROUP(scifb2_clk),
3987	SH_PFC_PIN_GROUP(scifb2_ctrl),
3988	SH_PFC_PIN_GROUP(scifb2_data_b),
3989	SH_PFC_PIN_GROUP(scifb2_clk_b),
3990	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3991	SH_PFC_PIN_GROUP(scifb2_data_c),
3992	SH_PFC_PIN_GROUP(sdhi0_data1),
3993	SH_PFC_PIN_GROUP(sdhi0_data4),
3994	SH_PFC_PIN_GROUP(sdhi0_ctrl),
3995	SH_PFC_PIN_GROUP(sdhi0_cd),
3996	SH_PFC_PIN_GROUP(sdhi0_wp),
3997	SH_PFC_PIN_GROUP(sdhi1_data1),
3998	SH_PFC_PIN_GROUP(sdhi1_data4),
3999	SH_PFC_PIN_GROUP(sdhi1_ctrl),
4000	SH_PFC_PIN_GROUP(sdhi1_cd),
4001	SH_PFC_PIN_GROUP(sdhi1_wp),
4002	SH_PFC_PIN_GROUP(sdhi2_data1),
4003	SH_PFC_PIN_GROUP(sdhi2_data4),
4004	SH_PFC_PIN_GROUP(sdhi2_ctrl),
4005	SH_PFC_PIN_GROUP(sdhi2_cd),
4006	SH_PFC_PIN_GROUP(sdhi2_wp),
4007	SH_PFC_PIN_GROUP(sdhi3_data1),
4008	SH_PFC_PIN_GROUP(sdhi3_data4),
4009	SH_PFC_PIN_GROUP(sdhi3_ctrl),
4010	SH_PFC_PIN_GROUP(sdhi3_cd),
4011	SH_PFC_PIN_GROUP(sdhi3_wp),
4012	SH_PFC_PIN_GROUP(ssi0_data),
4013	SH_PFC_PIN_GROUP(ssi0129_ctrl),
4014	SH_PFC_PIN_GROUP(ssi1_data),
4015	SH_PFC_PIN_GROUP(ssi1_ctrl),
4016	SH_PFC_PIN_GROUP(ssi2_data),
4017	SH_PFC_PIN_GROUP(ssi2_ctrl),
4018	SH_PFC_PIN_GROUP(ssi3_data),
4019	SH_PFC_PIN_GROUP(ssi34_ctrl),
4020	SH_PFC_PIN_GROUP(ssi4_data),
4021	SH_PFC_PIN_GROUP(ssi4_ctrl),
4022	SH_PFC_PIN_GROUP(ssi5),
4023	SH_PFC_PIN_GROUP(ssi5_b),
4024	SH_PFC_PIN_GROUP(ssi5_c),
4025	SH_PFC_PIN_GROUP(ssi6),
4026	SH_PFC_PIN_GROUP(ssi6_b),
4027	SH_PFC_PIN_GROUP(ssi7_data),
4028	SH_PFC_PIN_GROUP(ssi7_b_data),
4029	SH_PFC_PIN_GROUP(ssi7_c_data),
4030	SH_PFC_PIN_GROUP(ssi78_ctrl),
4031	SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4032	SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4033	SH_PFC_PIN_GROUP(ssi8_data),
4034	SH_PFC_PIN_GROUP(ssi8_b_data),
4035	SH_PFC_PIN_GROUP(ssi8_c_data),
4036	SH_PFC_PIN_GROUP(ssi9_data),
4037	SH_PFC_PIN_GROUP(ssi9_ctrl),
4038	SH_PFC_PIN_GROUP(tpu0_to0),
4039	SH_PFC_PIN_GROUP(tpu0_to1),
4040	SH_PFC_PIN_GROUP(tpu0_to2),
4041	SH_PFC_PIN_GROUP(tpu0_to3),
4042	SH_PFC_PIN_GROUP(usb0),
4043	SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4044	SH_PFC_PIN_GROUP(usb1),
4045	SH_PFC_PIN_GROUP(usb2),
4046	VIN_DATA_PIN_GROUP(vin0_data, 24),
4047	VIN_DATA_PIN_GROUP(vin0_data, 20),
4048	SH_PFC_PIN_GROUP(vin0_data18),
4049	VIN_DATA_PIN_GROUP(vin0_data, 16),
4050	VIN_DATA_PIN_GROUP(vin0_data, 12),
4051	VIN_DATA_PIN_GROUP(vin0_data, 10),
4052	VIN_DATA_PIN_GROUP(vin0_data, 8),
4053	VIN_DATA_PIN_GROUP(vin0_data, 4),
4054	SH_PFC_PIN_GROUP(vin0_sync),
4055	SH_PFC_PIN_GROUP(vin0_field),
4056	SH_PFC_PIN_GROUP(vin0_clkenb),
4057	SH_PFC_PIN_GROUP(vin0_clk),
4058	VIN_DATA_PIN_GROUP(vin1_data, 24),
4059	VIN_DATA_PIN_GROUP(vin1_data, 20),
4060	SH_PFC_PIN_GROUP(vin1_data18),
4061	VIN_DATA_PIN_GROUP(vin1_data, 16),
4062	VIN_DATA_PIN_GROUP(vin1_data, 12),
4063	VIN_DATA_PIN_GROUP(vin1_data, 10),
4064	VIN_DATA_PIN_GROUP(vin1_data, 8),
4065	VIN_DATA_PIN_GROUP(vin1_data, 4),
4066	SH_PFC_PIN_GROUP(vin1_sync),
4067	SH_PFC_PIN_GROUP(vin1_field),
4068	SH_PFC_PIN_GROUP(vin1_clkenb),
4069	SH_PFC_PIN_GROUP(vin1_clk),
4070	VIN_DATA_PIN_GROUP(vin2_data, 24),
4071	SH_PFC_PIN_GROUP(vin2_data18),
4072	VIN_DATA_PIN_GROUP(vin2_data, 16),
4073	VIN_DATA_PIN_GROUP(vin2_data, 8),
4074	VIN_DATA_PIN_GROUP(vin2_data, 4),
4075	SH_PFC_PIN_GROUP(vin2_sync),
4076	SH_PFC_PIN_GROUP(vin2_field),
4077	SH_PFC_PIN_GROUP(vin2_clkenb),
4078	SH_PFC_PIN_GROUP(vin2_clk),
4079	SH_PFC_PIN_GROUP(vin3_data8),
4080	SH_PFC_PIN_GROUP(vin3_sync),
4081	SH_PFC_PIN_GROUP(vin3_field),
4082	SH_PFC_PIN_GROUP(vin3_clkenb),
4083	SH_PFC_PIN_GROUP(vin3_clk),
4084};
4085
4086static const char * const audio_clk_groups[] = {
4087	"audio_clk_a",
4088	"audio_clk_b",
4089	"audio_clk_c",
4090	"audio_clkout",
4091	"audio_clkout_b",
4092	"audio_clkout_c",
4093	"audio_clkout_d",
4094};
4095
4096static const char * const du_groups[] = {
4097	"du_rgb666",
4098	"du_rgb888",
4099	"du_clk_out_0",
4100	"du_clk_out_1",
4101	"du_sync_0",
4102	"du_sync_1",
4103	"du_cde",
4104};
4105
4106static const char * const du0_groups[] = {
4107	"du0_clk_in",
4108};
4109
4110static const char * const du1_groups[] = {
4111	"du1_clk_in",
4112};
4113
4114static const char * const du2_groups[] = {
4115	"du2_clk_in",
4116};
4117
4118static const char * const eth_groups[] = {
4119	"eth_link",
4120	"eth_magic",
4121	"eth_mdio",
4122	"eth_rmii",
4123};
4124
4125static const char * const hscif0_groups[] = {
4126	"hscif0_data",
4127	"hscif0_clk",
4128	"hscif0_ctrl",
4129	"hscif0_data_b",
4130	"hscif0_ctrl_b",
4131	"hscif0_data_c",
4132	"hscif0_ctrl_c",
4133	"hscif0_data_d",
4134	"hscif0_ctrl_d",
4135	"hscif0_data_e",
4136	"hscif0_ctrl_e",
4137	"hscif0_data_f",
4138	"hscif0_ctrl_f",
4139};
4140
4141static const char * const hscif1_groups[] = {
4142	"hscif1_data",
4143	"hscif1_clk",
4144	"hscif1_ctrl",
4145	"hscif1_data_b",
4146	"hscif1_clk_b",
4147	"hscif1_ctrl_b",
4148};
4149
4150static const char * const i2c0_groups[] = {
4151	"i2c0",
4152};
4153
4154static const char * const i2c1_groups[] = {
4155	"i2c1",
4156	"i2c1_b",
4157	"i2c1_c",
4158};
4159
4160static const char * const i2c2_groups[] = {
4161	"i2c2",
4162	"i2c2_b",
4163	"i2c2_c",
4164	"i2c2_d",
4165	"i2c2_e",
4166};
4167
4168static const char * const i2c3_groups[] = {
4169	"i2c3",
4170};
4171
4172static const char * const iic0_groups[] = {
4173	"iic0",
4174};
4175
4176static const char * const iic1_groups[] = {
4177	"iic1",
4178	"iic1_b",
4179	"iic1_c",
4180};
4181
4182static const char * const iic2_groups[] = {
4183	"iic2",
4184	"iic2_b",
4185	"iic2_c",
4186	"iic2_d",
4187	"iic2_e",
4188};
4189
4190static const char * const iic3_groups[] = {
4191	"iic3",
4192};
4193
4194static const char * const intc_groups[] = {
4195	"intc_irq0",
4196	"intc_irq1",
4197	"intc_irq2",
4198	"intc_irq3",
4199};
4200
4201static const char * const mmc0_groups[] = {
4202	"mmc0_data1",
4203	"mmc0_data4",
4204	"mmc0_data8",
4205	"mmc0_ctrl",
4206};
4207
4208static const char * const mmc1_groups[] = {
4209	"mmc1_data1",
4210	"mmc1_data4",
4211	"mmc1_data8",
4212	"mmc1_ctrl",
4213};
4214
4215static const char * const msiof0_groups[] = {
4216	"msiof0_clk",
4217	"msiof0_sync",
4218	"msiof0_ss1",
4219	"msiof0_ss2",
4220	"msiof0_rx",
4221	"msiof0_tx",
4222	"msiof0_clk_b",
4223	"msiof0_ss1_b",
4224	"msiof0_ss2_b",
4225	"msiof0_rx_b",
4226	"msiof0_tx_b",
4227};
4228
4229static const char * const msiof1_groups[] = {
4230	"msiof1_clk",
4231	"msiof1_sync",
4232	"msiof1_ss1",
4233	"msiof1_ss2",
4234	"msiof1_rx",
4235	"msiof1_tx",
4236	"msiof1_clk_b",
4237	"msiof1_ss1_b",
4238	"msiof1_ss2_b",
4239	"msiof1_rx_b",
4240	"msiof1_tx_b",
4241};
4242
4243static const char * const msiof2_groups[] = {
4244	"msiof2_clk",
4245	"msiof2_sync",
4246	"msiof2_ss1",
4247	"msiof2_ss2",
4248	"msiof2_rx",
4249	"msiof2_tx",
4250};
4251
4252static const char * const msiof3_groups[] = {
4253	"msiof3_clk",
4254	"msiof3_sync",
4255	"msiof3_ss1",
4256	"msiof3_ss2",
4257	"msiof3_rx",
4258	"msiof3_tx",
4259	"msiof3_clk_b",
4260	"msiof3_sync_b",
4261	"msiof3_rx_b",
4262	"msiof3_tx_b",
4263};
4264
4265static const char * const qspi_groups[] = {
4266	"qspi_ctrl",
4267	"qspi_data2",
4268	"qspi_data4",
4269};
4270
4271static const char * const scif0_groups[] = {
4272	"scif0_data",
4273	"scif0_clk",
4274	"scif0_ctrl",
4275	"scif0_data_b",
4276};
4277
4278static const char * const scif1_groups[] = {
4279	"scif1_data",
4280	"scif1_clk",
4281	"scif1_ctrl",
4282	"scif1_data_b",
4283	"scif1_data_c",
4284	"scif1_data_d",
4285	"scif1_clk_d",
4286	"scif1_data_e",
4287	"scif1_clk_e",
4288};
4289
4290static const char * const scif2_groups[] = {
4291	"scif2_data",
4292	"scif2_clk",
4293	"scif2_data_b",
4294};
4295
4296static const char * const scifa0_groups[] = {
4297	"scifa0_data",
4298	"scifa0_clk",
4299	"scifa0_ctrl",
4300	"scifa0_data_b",
4301	"scifa0_clk_b",
4302	"scifa0_ctrl_b",
4303};
4304
4305static const char * const scifa1_groups[] = {
4306	"scifa1_data",
4307	"scifa1_clk",
4308	"scifa1_ctrl",
4309	"scifa1_data_b",
4310	"scifa1_clk_b",
4311	"scifa1_ctrl_b",
4312	"scifa1_data_c",
4313	"scifa1_clk_c",
4314	"scifa1_ctrl_c",
4315	"scifa1_data_d",
4316	"scifa1_clk_d",
4317	"scifa1_ctrl_d",
4318};
4319
4320static const char * const scifa2_groups[] = {
4321	"scifa2_data",
4322	"scifa2_clk",
4323	"scifa2_ctrl",
4324	"scifa2_data_b",
4325	"scifa2_data_c",
4326	"scifa2_clk_c",
4327};
4328
4329static const char * const scifb0_groups[] = {
4330	"scifb0_data",
4331	"scifb0_clk",
4332	"scifb0_ctrl",
4333	"scifb0_data_b",
4334	"scifb0_clk_b",
4335	"scifb0_ctrl_b",
4336	"scifb0_data_c",
4337};
4338
4339static const char * const scifb1_groups[] = {
4340	"scifb1_data",
4341	"scifb1_clk",
4342	"scifb1_ctrl",
4343	"scifb1_data_b",
4344	"scifb1_clk_b",
4345	"scifb1_ctrl_b",
4346	"scifb1_data_c",
4347	"scifb1_data_d",
4348	"scifb1_data_e",
4349	"scifb1_clk_e",
4350	"scifb1_data_f",
4351	"scifb1_data_g",
4352	"scifb1_clk_g",
4353};
4354
4355static const char * const scifb2_groups[] = {
4356	"scifb2_data",
4357	"scifb2_clk",
4358	"scifb2_ctrl",
4359	"scifb2_data_b",
4360	"scifb2_clk_b",
4361	"scifb2_ctrl_b",
4362	"scifb2_data_c",
4363};
4364
4365static const char * const sdhi0_groups[] = {
4366	"sdhi0_data1",
4367	"sdhi0_data4",
4368	"sdhi0_ctrl",
4369	"sdhi0_cd",
4370	"sdhi0_wp",
4371};
4372
4373static const char * const sdhi1_groups[] = {
4374	"sdhi1_data1",
4375	"sdhi1_data4",
4376	"sdhi1_ctrl",
4377	"sdhi1_cd",
4378	"sdhi1_wp",
4379};
4380
4381static const char * const sdhi2_groups[] = {
4382	"sdhi2_data1",
4383	"sdhi2_data4",
4384	"sdhi2_ctrl",
4385	"sdhi2_cd",
4386	"sdhi2_wp",
4387};
4388
4389static const char * const sdhi3_groups[] = {
4390	"sdhi3_data1",
4391	"sdhi3_data4",
4392	"sdhi3_ctrl",
4393	"sdhi3_cd",
4394	"sdhi3_wp",
4395};
4396
4397static const char * const ssi_groups[] = {
4398	"ssi0_data",
4399	"ssi0129_ctrl",
4400	"ssi1_data",
4401	"ssi1_ctrl",
4402	"ssi2_data",
4403	"ssi2_ctrl",
4404	"ssi3_data",
4405	"ssi34_ctrl",
4406	"ssi4_data",
4407	"ssi4_ctrl",
4408	"ssi5",
4409	"ssi5_b",
4410	"ssi5_c",
4411	"ssi6",
4412	"ssi6_b",
4413	"ssi7_data",
4414	"ssi7_b_data",
4415	"ssi7_c_data",
4416	"ssi78_ctrl",
4417	"ssi78_b_ctrl",
4418	"ssi78_c_ctrl",
4419	"ssi8_data",
4420	"ssi8_b_data",
4421	"ssi8_c_data",
4422	"ssi9_data",
4423	"ssi9_ctrl",
4424};
4425
4426static const char * const tpu0_groups[] = {
4427	"tpu0_to0",
4428	"tpu0_to1",
4429	"tpu0_to2",
4430	"tpu0_to3",
4431};
4432
4433static const char * const usb0_groups[] = {
4434	"usb0",
4435	"usb0_ovc_vbus",
4436};
4437
4438static const char * const usb1_groups[] = {
4439	"usb1",
4440};
4441
4442static const char * const usb2_groups[] = {
4443	"usb2",
4444};
4445
4446static const char * const vin0_groups[] = {
4447	"vin0_data24",
4448	"vin0_data20",
4449	"vin0_data18",
4450	"vin0_data16",
4451	"vin0_data12",
4452	"vin0_data10",
4453	"vin0_data8",
4454	"vin0_data4",
4455	"vin0_sync",
4456	"vin0_field",
4457	"vin0_clkenb",
4458	"vin0_clk",
4459};
4460
4461static const char * const vin1_groups[] = {
4462	"vin1_data24",
4463	"vin1_data20",
4464	"vin1_data18",
4465	"vin1_data16",
4466	"vin1_data12",
4467	"vin1_data10",
4468	"vin1_data8",
4469	"vin1_data4",
4470	"vin1_sync",
4471	"vin1_field",
4472	"vin1_clkenb",
4473	"vin1_clk",
4474};
4475
4476static const char * const vin2_groups[] = {
4477	"vin2_data24",
4478	"vin2_data18",
4479	"vin2_data16",
4480	"vin2_data8",
4481	"vin2_data4",
4482	"vin2_sync",
4483	"vin2_field",
4484	"vin2_clkenb",
4485	"vin2_clk",
4486};
4487
4488static const char * const vin3_groups[] = {
4489	"vin3_data8",
4490	"vin3_sync",
4491	"vin3_field",
4492	"vin3_clkenb",
4493	"vin3_clk",
4494};
4495
4496static const struct sh_pfc_function pinmux_functions[] = {
4497	SH_PFC_FUNCTION(audio_clk),
4498	SH_PFC_FUNCTION(du),
4499	SH_PFC_FUNCTION(du0),
4500	SH_PFC_FUNCTION(du1),
4501	SH_PFC_FUNCTION(du2),
4502	SH_PFC_FUNCTION(eth),
4503	SH_PFC_FUNCTION(hscif0),
4504	SH_PFC_FUNCTION(hscif1),
4505	SH_PFC_FUNCTION(i2c0),
4506	SH_PFC_FUNCTION(i2c1),
4507	SH_PFC_FUNCTION(i2c2),
4508	SH_PFC_FUNCTION(i2c3),
4509	SH_PFC_FUNCTION(iic0),
4510	SH_PFC_FUNCTION(iic1),
4511	SH_PFC_FUNCTION(iic2),
4512	SH_PFC_FUNCTION(iic3),
4513	SH_PFC_FUNCTION(intc),
4514	SH_PFC_FUNCTION(mmc0),
4515	SH_PFC_FUNCTION(mmc1),
4516	SH_PFC_FUNCTION(msiof0),
4517	SH_PFC_FUNCTION(msiof1),
4518	SH_PFC_FUNCTION(msiof2),
4519	SH_PFC_FUNCTION(msiof3),
4520	SH_PFC_FUNCTION(qspi),
4521	SH_PFC_FUNCTION(scif0),
4522	SH_PFC_FUNCTION(scif1),
4523	SH_PFC_FUNCTION(scif2),
4524	SH_PFC_FUNCTION(scifa0),
4525	SH_PFC_FUNCTION(scifa1),
4526	SH_PFC_FUNCTION(scifa2),
4527	SH_PFC_FUNCTION(scifb0),
4528	SH_PFC_FUNCTION(scifb1),
4529	SH_PFC_FUNCTION(scifb2),
4530	SH_PFC_FUNCTION(sdhi0),
4531	SH_PFC_FUNCTION(sdhi1),
4532	SH_PFC_FUNCTION(sdhi2),
4533	SH_PFC_FUNCTION(sdhi3),
4534	SH_PFC_FUNCTION(ssi),
4535	SH_PFC_FUNCTION(tpu0),
4536	SH_PFC_FUNCTION(usb0),
4537	SH_PFC_FUNCTION(usb1),
4538	SH_PFC_FUNCTION(usb2),
4539	SH_PFC_FUNCTION(vin0),
4540	SH_PFC_FUNCTION(vin1),
4541	SH_PFC_FUNCTION(vin2),
4542	SH_PFC_FUNCTION(vin3),
4543};
4544
4545static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4546	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4547		GP_0_31_FN, FN_IP3_17_15,
4548		GP_0_30_FN, FN_IP3_14_12,
4549		GP_0_29_FN, FN_IP3_11_8,
4550		GP_0_28_FN, FN_IP3_7_4,
4551		GP_0_27_FN, FN_IP3_3_0,
4552		GP_0_26_FN, FN_IP2_28_26,
4553		GP_0_25_FN, FN_IP2_25_22,
4554		GP_0_24_FN, FN_IP2_21_18,
4555		GP_0_23_FN, FN_IP2_17_15,
4556		GP_0_22_FN, FN_IP2_14_12,
4557		GP_0_21_FN, FN_IP2_11_9,
4558		GP_0_20_FN, FN_IP2_8_6,
4559		GP_0_19_FN, FN_IP2_5_3,
4560		GP_0_18_FN, FN_IP2_2_0,
4561		GP_0_17_FN, FN_IP1_29_28,
4562		GP_0_16_FN, FN_IP1_27_26,
4563		GP_0_15_FN, FN_IP1_25_22,
4564		GP_0_14_FN, FN_IP1_21_18,
4565		GP_0_13_FN, FN_IP1_17_15,
4566		GP_0_12_FN, FN_IP1_14_12,
4567		GP_0_11_FN, FN_IP1_11_8,
4568		GP_0_10_FN, FN_IP1_7_4,
4569		GP_0_9_FN, FN_IP1_3_0,
4570		GP_0_8_FN, FN_IP0_30_27,
4571		GP_0_7_FN, FN_IP0_26_23,
4572		GP_0_6_FN, FN_IP0_22_20,
4573		GP_0_5_FN, FN_IP0_19_16,
4574		GP_0_4_FN, FN_IP0_15_12,
4575		GP_0_3_FN, FN_IP0_11_9,
4576		GP_0_2_FN, FN_IP0_8_6,
4577		GP_0_1_FN, FN_IP0_5_3,
4578		GP_0_0_FN, FN_IP0_2_0 }
4579	},
4580	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4581		0, 0,
4582		0, 0,
4583		GP_1_29_FN, FN_IP6_13_11,
4584		GP_1_28_FN, FN_IP6_10_9,
4585		GP_1_27_FN, FN_IP6_8_6,
4586		GP_1_26_FN, FN_IP6_5_3,
4587		GP_1_25_FN, FN_IP6_2_0,
4588		GP_1_24_FN, FN_IP5_29_27,
4589		GP_1_23_FN, FN_IP5_26_24,
4590		GP_1_22_FN, FN_IP5_23_21,
4591		GP_1_21_FN, FN_IP5_20_18,
4592		GP_1_20_FN, FN_IP5_17_15,
4593		GP_1_19_FN, FN_IP5_14_13,
4594		GP_1_18_FN, FN_IP5_12_10,
4595		GP_1_17_FN, FN_IP5_9_6,
4596		GP_1_16_FN, FN_IP5_5_3,
4597		GP_1_15_FN, FN_IP5_2_0,
4598		GP_1_14_FN, FN_IP4_29_27,
4599		GP_1_13_FN, FN_IP4_26_24,
4600		GP_1_12_FN, FN_IP4_23_21,
4601		GP_1_11_FN, FN_IP4_20_18,
4602		GP_1_10_FN, FN_IP4_17_15,
4603		GP_1_9_FN, FN_IP4_14_12,
4604		GP_1_8_FN, FN_IP4_11_9,
4605		GP_1_7_FN, FN_IP4_8_6,
4606		GP_1_6_FN, FN_IP4_5_3,
4607		GP_1_5_FN, FN_IP4_2_0,
4608		GP_1_4_FN, FN_IP3_31_29,
4609		GP_1_3_FN, FN_IP3_28_26,
4610		GP_1_2_FN, FN_IP3_25_23,
4611		GP_1_1_FN, FN_IP3_22_20,
4612		GP_1_0_FN, FN_IP3_19_18, }
4613	},
4614	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4615		0, 0,
4616		0, 0,
4617		GP_2_29_FN, FN_IP7_15_13,
4618		GP_2_28_FN, FN_IP7_12_10,
4619		GP_2_27_FN, FN_IP7_9_8,
4620		GP_2_26_FN, FN_IP7_7_6,
4621		GP_2_25_FN, FN_IP7_5_3,
4622		GP_2_24_FN, FN_IP7_2_0,
4623		GP_2_23_FN, FN_IP6_31_29,
4624		GP_2_22_FN, FN_IP6_28_26,
4625		GP_2_21_FN, FN_IP6_25_23,
4626		GP_2_20_FN, FN_IP6_22_20,
4627		GP_2_19_FN, FN_IP6_19_17,
4628		GP_2_18_FN, FN_IP6_16_14,
4629		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4630		GP_2_16_FN, FN_IP8_27,
4631		GP_2_15_FN, FN_IP8_26,
4632		GP_2_14_FN, FN_IP8_25_24,
4633		GP_2_13_FN, FN_IP8_23_22,
4634		GP_2_12_FN, FN_IP8_21_20,
4635		GP_2_11_FN, FN_IP8_19_18,
4636		GP_2_10_FN, FN_IP8_17_16,
4637		GP_2_9_FN, FN_IP8_15_14,
4638		GP_2_8_FN, FN_IP8_13_12,
4639		GP_2_7_FN, FN_IP8_11_10,
4640		GP_2_6_FN, FN_IP8_9_8,
4641		GP_2_5_FN, FN_IP8_7_6,
4642		GP_2_4_FN, FN_IP8_5_4,
4643		GP_2_3_FN, FN_IP8_3_2,
4644		GP_2_2_FN, FN_IP8_1_0,
4645		GP_2_1_FN, FN_IP7_30_29,
4646		GP_2_0_FN, FN_IP7_28_27 }
4647	},
4648	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4649		GP_3_31_FN, FN_IP11_21_18,
4650		GP_3_30_FN, FN_IP11_17_15,
4651		GP_3_29_FN, FN_IP11_14_13,
4652		GP_3_28_FN, FN_IP11_12_11,
4653		GP_3_27_FN, FN_IP11_10_9,
4654		GP_3_26_FN, FN_IP11_8_7,
4655		GP_3_25_FN, FN_IP11_6_5,
4656		GP_3_24_FN, FN_IP11_4,
4657		GP_3_23_FN, FN_IP11_3_0,
4658		GP_3_22_FN, FN_IP10_29_26,
4659		GP_3_21_FN, FN_IP10_25_23,
4660		GP_3_20_FN, FN_IP10_22_19,
4661		GP_3_19_FN, FN_IP10_18_15,
4662		GP_3_18_FN, FN_IP10_14_11,
4663		GP_3_17_FN, FN_IP10_10_7,
4664		GP_3_16_FN, FN_IP10_6_4,
4665		GP_3_15_FN, FN_IP10_3_0,
4666		GP_3_14_FN, FN_IP9_31_28,
4667		GP_3_13_FN, FN_IP9_27_26,
4668		GP_3_12_FN, FN_IP9_25_24,
4669		GP_3_11_FN, FN_IP9_23_22,
4670		GP_3_10_FN, FN_IP9_21_20,
4671		GP_3_9_FN, FN_IP9_19_18,
4672		GP_3_8_FN, FN_IP9_17_16,
4673		GP_3_7_FN, FN_IP9_15_12,
4674		GP_3_6_FN, FN_IP9_11_8,
4675		GP_3_5_FN, FN_IP9_7_6,
4676		GP_3_4_FN, FN_IP9_5_4,
4677		GP_3_3_FN, FN_IP9_3_2,
4678		GP_3_2_FN, FN_IP9_1_0,
4679		GP_3_1_FN, FN_IP8_30_29,
4680		GP_3_0_FN, FN_IP8_28 }
4681	},
4682	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4683		GP_4_31_FN, FN_IP14_18_16,
4684		GP_4_30_FN, FN_IP14_15_12,
4685		GP_4_29_FN, FN_IP14_11_9,
4686		GP_4_28_FN, FN_IP14_8_6,
4687		GP_4_27_FN, FN_IP14_5_3,
4688		GP_4_26_FN, FN_IP14_2_0,
4689		GP_4_25_FN, FN_IP13_30_29,
4690		GP_4_24_FN, FN_IP13_28_26,
4691		GP_4_23_FN, FN_IP13_25_23,
4692		GP_4_22_FN, FN_IP13_22_19,
4693		GP_4_21_FN, FN_IP13_18_16,
4694		GP_4_20_FN, FN_IP13_15_13,
4695		GP_4_19_FN, FN_IP13_12_10,
4696		GP_4_18_FN, FN_IP13_9_7,
4697		GP_4_17_FN, FN_IP13_6_3,
4698		GP_4_16_FN, FN_IP13_2_0,
4699		GP_4_15_FN, FN_IP12_30_28,
4700		GP_4_14_FN, FN_IP12_27_25,
4701		GP_4_13_FN, FN_IP12_24_23,
4702		GP_4_12_FN, FN_IP12_22_20,
4703		GP_4_11_FN, FN_IP12_19_17,
4704		GP_4_10_FN, FN_IP12_16_14,
4705		GP_4_9_FN, FN_IP12_13_11,
4706		GP_4_8_FN, FN_IP12_10_8,
4707		GP_4_7_FN, FN_IP12_7_6,
4708		GP_4_6_FN, FN_IP12_5_4,
4709		GP_4_5_FN, FN_IP12_3_2,
4710		GP_4_4_FN, FN_IP12_1_0,
4711		GP_4_3_FN, FN_IP11_31_30,
4712		GP_4_2_FN, FN_IP11_29_27,
4713		GP_4_1_FN, FN_IP11_26_24,
4714		GP_4_0_FN, FN_IP11_23_22 }
4715	},
4716	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4717		GP_5_31_FN, FN_IP7_24_22,
4718		GP_5_30_FN, FN_IP7_21_19,
4719		GP_5_29_FN, FN_IP7_18_16,
4720		GP_5_28_FN, FN_DU_DOTCLKIN2,
4721		GP_5_27_FN, FN_IP7_26_25,
4722		GP_5_26_FN, FN_DU_DOTCLKIN0,
4723		GP_5_25_FN, FN_AVS2,
4724		GP_5_24_FN, FN_AVS1,
4725		GP_5_23_FN, FN_USB2_OVC,
4726		GP_5_22_FN, FN_USB2_PWEN,
4727		GP_5_21_FN, FN_IP16_7,
4728		GP_5_20_FN, FN_IP16_6,
4729		GP_5_19_FN, FN_USB0_OVC_VBUS,
4730		GP_5_18_FN, FN_USB0_PWEN,
4731		GP_5_17_FN, FN_IP16_5_3,
4732		GP_5_16_FN, FN_IP16_2_0,
4733		GP_5_15_FN, FN_IP15_29_28,
4734		GP_5_14_FN, FN_IP15_27_26,
4735		GP_5_13_FN, FN_IP15_25_23,
4736		GP_5_12_FN, FN_IP15_22_20,
4737		GP_5_11_FN, FN_IP15_19_18,
4738		GP_5_10_FN, FN_IP15_17_16,
4739		GP_5_9_FN, FN_IP15_15_14,
4740		GP_5_8_FN, FN_IP15_13_12,
4741		GP_5_7_FN, FN_IP15_11_9,
4742		GP_5_6_FN, FN_IP15_8_6,
4743		GP_5_5_FN, FN_IP15_5_3,
4744		GP_5_4_FN, FN_IP15_2_0,
4745		GP_5_3_FN, FN_IP14_30_28,
4746		GP_5_2_FN, FN_IP14_27_25,
4747		GP_5_1_FN, FN_IP14_24_22,
4748		GP_5_0_FN, FN_IP14_21_19 }
4749	},
4750	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4751			     1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4752		/* IP0_31 [1] */
4753		0, 0,
4754		/* IP0_30_27 [4] */
4755		FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
4756		FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4757		0, 0, 0, 0, 0, 0, 0, 0, 0,
4758		/* IP0_26_23 [4] */
4759		FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4760		FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
4761		FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
4762		/* IP0_22_20 [3] */
4763		FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4764		FN_I2C2_SCL_C, 0, 0,
4765		/* IP0_19_16 [4] */
4766		FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4767		FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4768		0, 0, 0, 0, 0, 0, 0, 0, 0,
4769		/* IP0_15_12 [4] */
4770		FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4771		FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4772		0, 0, 0, 0, 0, 0, 0, 0, 0,
4773		/* IP0_11_9 [3] */
4774		FN_D3, FN_MSIOF3_TXD_B,	FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4775		0, 0, 0,
4776		/* IP0_8_6 [3] */
4777		FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4778		0, 0, 0,
4779		/* IP0_5_3 [3] */
4780		FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
4781		0, 0, 0,
4782		/* IP0_2_0 [3] */
4783		FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4784		0, 0, 0, }
4785	},
4786	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4787			     2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4788		/* IP1_31_30 [2] */
4789		0, 0, 0, 0,
4790		/* IP1_29_28 [2] */
4791		FN_A1, FN_PWM4, 0, 0,
4792		/* IP1_27_26 [2] */
4793		FN_A0, FN_PWM3, 0, 0,
4794		/* IP1_25_22 [4] */
4795		FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
4796		FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
4797		0, 0, 0, 0, 0, 0, 0, 0, 0,
4798		/* IP1_21_18 [4] */
4799		FN_D14,	FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
4800		FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
4801		0, 0, 0, 0, 0, 0, 0, 0, 0,
4802		/* IP1_17_15 [3] */
4803		FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
4804		FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
4805		0, 0, 0,
4806		/* IP1_14_12 [3] */
4807		FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
4808		FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
4809		0, 0,
4810		/* IP1_11_8 [4] */
4811		FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
4812		FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
4813		0, 0, 0, 0, 0, 0, 0, 0, 0,
4814		/* IP1_7_4 [4] */
4815		FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
4816		FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
4817		0, 0, 0, 0, 0, 0, 0, 0, 0,
4818		/* IP1_3_0 [4] */
4819		FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
4820		FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
4821		0, 0, 0, 0, 0, 0, 0, 0, 0, }
4822	},
4823	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4824			     3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
4825		/* IP2_31_29 [3] */
4826		0, 0, 0, 0, 0, 0, 0, 0,
4827		/* IP2_28_26 [3] */
4828		FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
4829		FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
4830		/* IP2_25_22 [4] */
4831		FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
4832		FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
4833		0, 0, 0, 0, 0, 0, 0, 0,
4834		/* IP2_21_18 [4] */
4835		FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
4836		FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
4837		0, 0, 0, 0, 0, 0, 0, 0,
4838		/* IP2_17_15 [3] */
4839		FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
4840		0, 0, 0, 0,
4841		/* IP2_14_12 [3] */
4842		FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
4843		/* IP2_11_9 [3] */
4844		FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
4845		/* IP2_8_6 [3] */
4846		FN_A4, FN_MSIOF1_TXD_B,	FN_TPU0TO0, 0, 0, 0, 0, 0,
4847		/* IP2_5_3 [3] */
4848		FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
4849		/* IP2_2_0 [3] */
4850		FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0,	}
4851	},
4852	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4853			     3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
4854		/* IP3_31_29 [3] */
4855		FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
4856		0, 0, 0,
4857		/* IP3_28_26 [3] */
4858		FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
4859		0, 0, 0, 0,
4860		/* IP3_25_23 [3] */
4861		FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
4862		/* IP3_22_20 [3] */
4863		FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
4864		/* IP3_19_18 [2] */
4865		FN_A16, FN_ATAWR1_N, 0, 0,
4866		/* IP3_17_15 [3] */
4867		FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
4868		0, 0, 0, 0,
4869		/* IP3_14_12 [3] */
4870		FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
4871		0, 0, 0, 0,
4872		/* IP3_11_8 [4] */
4873		FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
4874		FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
4875		FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
4876		/* IP3_7_4 [4] */
4877		FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
4878		FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
4879		0, 0, 0, 0, 0, 0, 0, 0, 0,
4880		/* IP3_3_0 [4] */
4881		FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
4882		FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
4883		0, 0, 0, 0, 0, 0, 0, 0, }
4884	},
4885	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4886			     2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4887		/* IP4_31_30 [2] */
4888		0, 0, 0, 0,
4889		/* IP4_29_27 [3] */
4890		FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
4891		FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
4892		/* IP4_26_24 [3] */
4893		FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
4894		FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
4895		/* IP4_23_21 [3] */
4896		FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
4897		FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
4898		/* IP4_20_18 [3] */
4899		FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
4900		FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
4901		/* IP4_17_15 [3] */
4902		FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
4903		0, 0, 0,
4904		/* IP4_14_12 [3] */
4905		FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
4906		FN_VI2_FIELD_B, 0, 0,
4907		/* IP4_11_9 [3] */
4908		FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
4909		FN_VI2_CLKENB_B, 0, 0,
4910		/* IP4_8_6 [3] */
4911		FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
4912		/* IP4_5_3 [3] */
4913		FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
4914		/* IP4_2_0 [3] */
4915		FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
4916		}
4917	},
4918	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4919			     2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
4920		/* IP5_31_30 [2] */
4921		0, 0, 0, 0,
4922		/* IP5_29_27 [3] */
4923		FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
4924		FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
4925		/* IP5_26_24 [3] */
4926		FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
4927		FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
4928		FN_MSIOF0_SCK_B, 0,
4929		/* IP5_23_21 [3] */
4930		FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
4931		FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
4932		/* IP5_20_18 [3] */
4933		FN_WE0_N, FN_IECLK, FN_CAN_CLK,
4934		FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
4935		/* IP5_17_15 [3] */
4936		FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
4937		FN_INTC_IRQ4_N, 0, 0,
4938		/* IP5_14_13 [2] */
4939		FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
4940		/* IP5_12_10 [3] */
4941		FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
4942		0, 0,
4943		/* IP5_9_6 [4] */
4944		FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
4945		FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
4946		FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
4947		/* IP5_5_3 [3] */
4948		FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
4949		FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
4950		FN_INTC_EN0_N, FN_I2C1_SCL,
4951		/* IP5_2_0 [3] */
4952		FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
4953		FN_VI2_R3, 0, 0, }
4954	},
4955	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4956			     3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
4957		/* IP6_31_29 [3] */
4958		FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
4959		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
4960		/* IP6_28_26 [3] */
4961		FN_ETH_LINK, 0, FN_HTX0_E,
4962		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
4963		/* IP6_25_23 [3] */
4964		FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
4965		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
4966		/* IP6_22_20 [3] */
4967		FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
4968		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
4969		/* IP6_19_17 [3] */
4970		FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
4971		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
4972		/* IP6_16_14 [3] */
4973		FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
4974		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
4975		FN_I2C2_SCL_E, 0,
4976		/* IP6_13_11 [3] */
4977		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
4978		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
4979		/* IP6_10_9 [2] */
4980		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
4981		/* IP6_8_6 [3] */
4982		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
4983		FN_SSI_SDATA8_C, 0, 0, 0,
4984		/* IP6_5_3 [3] */
4985		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
4986		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
4987		/* IP6_2_0 [3] */
4988		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
4989		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
4990	},
4991	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4992			     1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
4993		/* IP7_31 [1] */
4994		0, 0,
4995		/* IP7_30_29 [2] */
4996		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
4997		/* IP7_28_27 [2] */
4998		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
4999		/* IP7_26_25 [2] */
5000		FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5001		/* IP7_24_22 [3] */
5002		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5003		0, 0, 0,
5004		/* IP7_21_19 [3] */
5005		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5006		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5007		/* IP7_18_16 [3] */
5008		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5009		FN_GLO_SS_C, 0, 0, 0,
5010		/* IP7_15_13 [3] */
5011		FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5012		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5013		/* IP7_12_10 [3] */
5014		FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5015		FN_GLO_SCLK_C, 0, 0, 0,
5016		/* IP7_9_8 [2] */
5017		FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5018		/* IP7_7_6 [2] */
5019		FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5020		/* IP7_5_3 [3] */
5021		FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5022		/* IP7_2_0 [3] */
5023		FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5024		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
5025	},
5026	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5027			     1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5028			     2, 2, 2, 2, 2, 2, 2) {
5029		/* IP8_31 [1] */
5030		0, 0,
5031		/* IP8_30_29 [2] */
5032		FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5033		/* IP8_28 [1] */
5034		FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5035		/* IP8_27 [1] */
5036		FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5037		/* IP8_26 [1] */
5038		FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5039		/* IP8_25_24 [2] */
5040		FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5041		FN_AVB_MAGIC, 0,
5042		/* IP8_23_22 [2] */
5043		FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5044		/* IP8_21_20 [2] */
5045		FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5046		/* IP8_19_18 [2] */
5047		FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5048		/* IP8_17_16 [2] */
5049		FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5050		/* IP8_15_14 [2] */
5051		FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5052		/* IP8_13_12 [2] */
5053		FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5054		/* IP8_11_10 [2] */
5055		FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5056		/* IP8_9_8 [2] */
5057		FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5058		/* IP8_7_6 [2] */
5059		FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5060		/* IP8_5_4 [2] */
5061		FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5062		/* IP8_3_2 [2] */
5063		FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5064		/* IP8_1_0 [2] */
5065		FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
5066	},
5067	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5068			     4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5069		/* IP9_31_28 [4] */
5070		FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5071		FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5072		FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5073		/* IP9_27_26 [2] */
5074		FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5075		/* IP9_25_24 [2] */
5076		FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5077		/* IP9_23_22 [2] */
5078		FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5079		/* IP9_21_20 [2] */
5080		FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5081		/* IP9_19_18 [2] */
5082		FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5083		/* IP9_17_16 [2] */
5084		FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5085		/* IP9_15_12 [4] */
5086		FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5087		FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5088		FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5089		/* IP9_11_8 [4] */
5090		FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5091		FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5092		FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5093		/* IP9_7_6 [2] */
5094		FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5095		/* IP9_5_4 [2] */
5096		FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5097		/* IP9_3_2 [2] */
5098		FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5099		/* IP9_1_0 [2] */
5100		FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
5101	},
5102	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5103			     2, 4, 3, 4, 4, 4, 4, 3, 4) {
5104		/* IP10_31_30 [2] */
5105		0, 0, 0, 0,
5106		/* IP10_29_26 [4] */
5107		FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5108		FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5109		FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5110		/* IP10_25_23 [3] */
5111		FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5112		FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5113		/* IP10_22_19 [4] */
5114		FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5115		FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5116		FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5117		/* IP10_18_15 [4] */
5118		FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5119		FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5120		FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5121		0, 0, 0, 0, 0, 0,
5122		/* IP10_14_11 [4] */
5123		FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5124		FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5125		FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5126		0, 0, 0, 0, 0, 0, 0,
5127		/* IP10_10_7 [4] */
5128		FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5129		FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5130		FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5131		0, 0, 0, 0, 0, 0, 0,
5132		/* IP10_6_4 [3] */
5133		FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5134		FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5135		FN_VI3_DATA0_B, 0,
5136		/* IP10_3_0 [4] */
5137		FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5138		FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5139		FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
5140	},
5141	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5142			     2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
5143		/* IP11_31_30 [2] */
5144		FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5145		/* IP11_29_27 [3] */
5146		FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5147		0, 0, 0,
5148		/* IP11_26_24 [3] */
5149		FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5150		0, 0, 0,
5151		/* IP11_23_22 [2] */
5152		FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5153		/* IP11_21_18 [4] */
5154		FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5155		0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5156		/* IP11_17_15 [3] */
5157		FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5158		FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5159		/* IP11_14_13 [2] */
5160		FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5161		/* IP11_12_11 [2] */
5162		FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5163		/* IP11_10_9 [2] */
5164		FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5165		/* IP11_8_7 [2] */
5166		FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5167		/* IP11_6_5 [2] */
5168		FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5169		/* IP11_4 [1] */
5170		FN_SD3_CLK, FN_MMC1_CLK,
5171		/* IP11_3_0 [4] */
5172		FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5173		FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5174		FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
5175	},
5176	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5177			     1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5178		/* IP12_31 [1] */
5179		0, 0,
5180		/* IP12_30_28 [3] */
5181		FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5182		FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5183		FN_CAN_DEBUGOUT4, 0, 0,
5184		/* IP12_27_25 [3] */
5185		FN_SSI_SCK5, FN_SCIFB1_SCK,
5186		FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5187		FN_CAN_DEBUGOUT3, 0, 0,
5188		/* IP12_24_23 [2] */
5189		FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5190		FN_CAN_DEBUGOUT2,
5191		/* IP12_22_20 [3] */
5192		FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5193		FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5194		/* IP12_19_17 [3] */
5195		FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5196		FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5197		/* IP12_16_14 [3] */
5198		FN_SSI_SDATA3, FN_STP_ISCLK_0,
5199		FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5200		/* IP12_13_11 [3] */
5201		FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5202		FN_CAN_STEP0, 0, 0, 0,
5203		/* IP12_10_8 [3] */
5204		FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5205		FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5206		/* IP12_7_6 [2] */
5207		FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5208		/* IP12_5_4 [2] */
5209		FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5210		/* IP12_3_2 [2] */
5211		FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5212		/* IP12_1_0 [2] */
5213		FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
5214	},
5215	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5216			     1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5217		/* IP13_31 [1] */
5218		0, 0,
5219		/* IP13_30_29 [2] */
5220		FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5221		/* IP13_28_26 [3] */
5222		FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5223		FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5224		/* IP13_25_23 [3] */
5225		FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5226		FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5227		/* IP13_22_19 [4] */
5228		FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5229		FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5230		0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5231		/* IP13_18_16 [3] */
5232		FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5233		FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5234		/* IP13_15_13 [3] */
5235		FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5236		FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5237		/* IP13_12_10 [3] */
5238		FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5239		FN_CAN_DEBUGOUT8, 0, 0,
5240		/* IP13_9_7 [3] */
5241		FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5242		FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5243		/* IP13_6_3 [4] */
5244		FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5245		FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5246		FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5247		/* IP13_2_0 [3] */
5248		FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5249		FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
5250	},
5251	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5252			     1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5253		/* IP14_30 [1] */
5254		0, 0,
5255		/* IP14_30_28 [3] */
5256		FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5257		FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5258		FN_HRTS0_N_C, 0,
5259		/* IP14_27_25 [3] */
5260		FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5261		FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5262		/* IP14_24_22 [3] */
5263		FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5264		FN_LCDOUT9, 0, 0, 0,
5265		/* IP14_21_19 [3] */
5266		FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5267		FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5268		/* IP14_18_16 [3] */
5269		FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5270		FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5271		/* IP14_15_12 [4] */
5272		FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5273		FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5274		0, 0, 0, 0, 0, 0, 0,
5275		/* IP14_11_9 [3] */
5276		FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5277		0, 0, 0,
5278		/* IP14_8_6 [3] */
5279		FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5280		0, 0, 0,
5281		/* IP14_5_3 [3] */
5282		FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5283		FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5284		/* IP14_2_0 [3] */
5285		FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5286		FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5287		FN_REMOCON, 0, }
5288	},
5289	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5290			     2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5291		/* IP15_31_30 [2] */
5292		0, 0, 0, 0,
5293		/* IP15_29_28 [2] */
5294		FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5295		/* IP15_27_26 [2] */
5296		FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5297		/* IP15_25_23 [3] */
5298		FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5299		FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5300		/* IP15_22_20 [3] */
5301		FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5302		FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5303		/* IP15_19_18 [2] */
5304		FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5305		/* IP15_17_16 [2] */
5306		FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5307		/* IP15_15_14 [2] */
5308		FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5309		/* IP15_13_12 [2] */
5310		FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5311		/* IP15_11_9 [3] */
5312		FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5313		0, 0, 0,
5314		/* IP15_8_6 [3] */
5315		FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5316		FN_IIC2_SDA, FN_I2C2_SDA, 0,
5317		/* IP15_5_3 [3] */
5318		FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5319		FN_IIC2_SCL, FN_I2C2_SCL, 0,
5320		/* IP15_2_0 [3] */
5321		FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5322		FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5323	},
5324	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5325			     4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5326		/* IP16_31_28 [4] */
5327		0, 0, 0, 0, 0, 0, 0, 0,
5328		0, 0, 0, 0, 0, 0, 0, 0,
5329		/* IP16_27_24 [4] */
5330		0, 0, 0, 0, 0, 0, 0, 0,
5331		0, 0, 0, 0, 0, 0, 0, 0,
5332		/* IP16_23_20 [4] */
5333		0, 0, 0, 0, 0, 0, 0, 0,
5334		0, 0, 0, 0, 0, 0, 0, 0,
5335		/* IP16_19_16 [4] */
5336		0, 0, 0, 0, 0, 0, 0, 0,
5337		0, 0, 0, 0, 0, 0, 0, 0,
5338		/* IP16_15_12 [4] */
5339		0, 0, 0, 0, 0, 0, 0, 0,
5340		0, 0, 0, 0, 0, 0, 0, 0,
5341		/* IP16_11_8 [4] */
5342		0, 0, 0, 0, 0, 0, 0, 0,
5343		0, 0, 0, 0, 0, 0, 0, 0,
5344		/* IP16_7 [1] */
5345		FN_USB1_OVC, FN_TCLK1_B,
5346		/* IP16_6 [1] */
5347		FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5348		/* IP16_5_3 [3] */
5349		FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5350		FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5351		/* IP16_2_0 [3] */
5352		FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5353		FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5354	},
5355	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5356			     3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5357			     2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5358		/* SEL_SCIF1 [3] */
5359		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5360		FN_SEL_SCIF1_4, 0, 0, 0,
5361		/* SEL_SCIFB [2] */
5362		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5363		/* SEL_SCIFB2 [2] */
5364		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5365		/* SEL_SCIFB1 [3] */
5366		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5367		FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5368		FN_SEL_SCIFB1_6, 0,
5369		/* SEL_SCIFA1 [2] */
5370		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5371		FN_SEL_SCIFA1_3,
5372		/* SEL_SCIF0 [1] */
5373		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5374		/* SEL_SCIFA [1] */
5375		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5376		/* SEL_SOF1 [1] */
5377		FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5378		/* SEL_SSI7 [2] */
5379		FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5380		/* SEL_SSI6 [1] */
5381		FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5382		/* SEL_SSI5 [2] */
5383		FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5384		/* SEL_VI3 [1] */
5385		FN_SEL_VI3_0, FN_SEL_VI3_1,
5386		/* SEL_VI2 [1] */
5387		FN_SEL_VI2_0, FN_SEL_VI2_1,
5388		/* SEL_VI1 [1] */
5389		FN_SEL_VI1_0, FN_SEL_VI1_1,
5390		/* SEL_VI0 [1] */
5391		FN_SEL_VI0_0, FN_SEL_VI0_1,
5392		/* SEL_TSIF1 [2] */
5393		FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5394		/* RESERVED [1] */
5395		0, 0,
5396		/* SEL_LBS [1] */
5397		FN_SEL_LBS_0, FN_SEL_LBS_1,
5398		/* SEL_TSIF0 [2] */
5399		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5400		/* SEL_SOF3 [1] */
5401		FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5402		/* SEL_SOF0 [1] */
5403		FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5404	},
5405	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5406			     3, 1, 1, 1, 2, 1, 2, 1, 2,
5407			     1, 1, 1, 3, 3, 2, 3, 2, 2) {
5408		/* RESERVED [3] */
5409		0, 0, 0, 0, 0, 0, 0, 0,
5410		/* SEL_TMU1 [1] */
5411		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5412		/* SEL_HSCIF1 [1] */
5413		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5414		/* SEL_SCIFCLK [1] */
5415		FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5416		/* SEL_CAN0 [2] */
5417		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5418		/* SEL_CANCLK [1] */
5419		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5420		/* SEL_SCIFA2 [2] */
5421		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5422		/* SEL_CAN1 [1] */
5423		FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5424		/* RESERVED [2] */
5425		0, 0, 0, 0,
5426		/* SEL_SCIF2 [1] */
5427		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5428		/* SEL_ADI [1] */
5429		FN_SEL_ADI_0, FN_SEL_ADI_1,
5430		/* SEL_SSP [1] */
5431		FN_SEL_SSP_0, FN_SEL_SSP_1,
5432		/* SEL_FM [3] */
5433		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5434		FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5435		/* SEL_HSCIF0 [3] */
5436		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5437		FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5438		/* SEL_GPS [2] */
5439		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5440		/* RESERVED [3] */
5441		0, 0, 0, 0, 0, 0, 0, 0,
5442		/* SEL_SIM [2] */
5443		FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5444		/* SEL_SSI8 [2] */
5445		FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5446	},
5447	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5448			     1, 1, 2, 4, 4, 2, 2,
5449			     4, 2, 3, 2, 3, 2) {
5450		/* SEL_IICDVFS [1] */
5451		FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5452		/* SEL_IIC0 [1] */
5453		FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5454		/* RESERVED [2] */
5455		0, 0, 0, 0,
5456		/* RESERVED [4] */
5457		0, 0, 0, 0, 0, 0, 0, 0,
5458		0, 0, 0, 0, 0, 0, 0, 0,
5459		/* RESERVED [4] */
5460		0, 0, 0, 0, 0, 0, 0, 0,
5461		0, 0, 0, 0, 0, 0, 0, 0,
5462		/* RESERVED [2] */
5463		0, 0, 0, 0,
5464		/* SEL_IEB [2] */
5465		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5466		/* RESERVED [4] */
5467		0, 0, 0, 0, 0, 0, 0, 0,
5468		0, 0, 0, 0, 0, 0, 0, 0,
5469		/* RESERVED [2] */
5470		0, 0, 0, 0,
5471		/* SEL_IIC2 [3] */
5472		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5473		FN_SEL_IIC2_4, 0, 0, 0,
5474		/* SEL_IIC1 [2] */
5475		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5476		/* SEL_I2C2 [3] */
5477		FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5478		FN_SEL_I2C2_4, 0, 0, 0,
5479		/* SEL_I2C1 [2] */
5480		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5481	},
5482	{ },
5483};
5484
5485const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5486	.name = "r8a77900_pfc",
5487	.unlock_reg = 0xe6060000, /* PMMR */
5488
5489	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5490
5491	.pins = pinmux_pins,
5492	.nr_pins = ARRAY_SIZE(pinmux_pins),
5493	.groups = pinmux_groups,
5494	.nr_groups = ARRAY_SIZE(pinmux_groups),
5495	.functions = pinmux_functions,
5496	.nr_functions = ARRAY_SIZE(pinmux_functions),
5497
5498	.cfg_regs = pinmux_config_regs,
5499
5500	.gpio_data = pinmux_data,
5501	.gpio_data_size = ARRAY_SIZE(pinmux_data),
5502};
5503