/drivers/gpu/drm/nouveau/ |
H A D | nv04_pm.c | 49 struct pll_lims pll; member in struct:nv04_pm_clock 63 ret = get_pll_limits(dev, id, &clk->pll); 67 ret = nouveau_calc_pll_mnp(dev, &clk->pll, khz, &clk->calc); 104 u32 reg = clk->pll.reg; 122 if (state->memory.pll.reg) {
|
H A D | nv50_calc.c | 30 nv50_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk, argument 36 ret = nouveau_calc_pll_mnp(dev, pll, clk, &pll_vals); 49 nva3_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk, argument 55 *P = pll->vco1.maxfreq / clk; 56 if (*P > pll->max_p) 57 *P = pll->max_p; 58 if (*P < pll->min_p) 59 *P = pll->min_p; 61 lM = (pll->refclk + pll [all...] |
H A D | nv40_pm.c | 109 nv40_calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, argument 115 ret = get_pll_limits(dev, reg, pll); 119 if (clk < pll->vco1.maxfreq) 120 pll->vco2.maxfreq = 0; 122 ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef); 129 if (pll->vco2.maxfreq) { 145 struct pll_lims pll; local 154 ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core, 169 ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader, 187 ret = nv40_calc_pll(dev, 0x004020, &pll, perflv [all...] |
H A D | nva3_pm.c | 79 read_pll(struct drm_device *dev, int clk, u32 pll) argument 81 u32 ctrl = nv_rd32(dev, pll + 0); 86 u32 coef = nv_rd32(dev, pll + 4); 92 if ((pll & 0x00ff00) == 0x00e800) 106 u32 pll; member in struct:creg 110 calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg) argument 117 reg->pll = 0; 120 NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk); 148 if (!pll || (diff >= -2000 && diff < 3000)) { 154 if (!pll) { 179 prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg) argument [all...] |
H A D | nvc0_pm.c | 43 read_pll(struct drm_device *dev, u32 pll) argument 45 u32 ctrl = nv_rd32(dev, pll + 0); 46 u32 coef = nv_rd32(dev, pll + 4); 55 switch (pll & 0xfff000) { 61 doff = (pll - 0x137000) / 0x20; 65 switch (pll) { 238 * P: pll 350 /* switch clock to non-pll mode */ 354 /* reprogram pll */ 372 /* select pll/no [all...] |
H A D | nv50_pm.c | 86 NV_ERROR(dev, "ref: bad pll 0x%06x\n", base); 114 NV_ERROR(dev, "ref: bad pll 0x%06x\n", base); 161 NV_ERROR(dev, "bad pll 0x%06x\n", base); 369 calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, argument 375 ret = get_pll_limits(dev, reg, pll); 379 pll->vco2.maxfreq = 0; 380 pll->refclk = read_pll_ref(dev, reg); 381 if (!pll->refclk) 384 ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef); 422 struct pll_lims pll; local 497 struct pll_lims pll; local [all...] |
H A D | nouveau_hw.c | 150 * stage pll 166 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; local 170 if (oldpll == pll) 193 NVWriteRAMDAC(dev, 0, reg, pll); 204 if (ss) /* single stage pll mode */ 515 * beyond the pll limits. for some reason this causes the chip to 516 * lock up when reading the dac palette regs, so set a valid pll here 522 enum pll_types pll = head ? PLL_VPLL1 : PLL_VPLL0; local 524 if (get_pll_limits(dev, pll, &pll_lim)) 526 nouveau_hw_get_pllvals(dev, pll, [all...] |
H A D | nv50_crtc.c | 298 struct pll_lims pll; local 302 ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll); 306 if (pll.vco2.maxfreq) { 307 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P); 314 reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00; 315 reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00; 316 nv_wr32(dev, pll.reg + 0, 0x10000611); 317 nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1); 318 nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2); 321 ret = nva3_calc_pll(dev, &pll, pcl [all...] |
/drivers/video/via/ |
H A D | via_clock.h | 63 struct via_pll_config pll) 65 return ref_freq / pll.divisor * pll.multiplier; 69 struct via_pll_config pll) 71 return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift; 62 get_pll_internal_frequency(u32 ref_freq, struct via_pll_config pll) argument 68 get_pll_output_frequency(u32 ref_freq, struct via_pll_config pll) argument
|
H A D | via_clock.c | 35 static inline u32 cle266_encode_pll(struct via_pll_config pll) argument 37 return (pll.multiplier << 8) 38 | (pll.rshift << 6) 39 | pll.divisor; 42 static inline u32 k800_encode_pll(struct via_pll_config pll) argument 44 return ((pll.divisor - 2) << 16) 45 | (pll.rshift << 10) 46 | (pll.multiplier - 2); 49 static inline u32 vx855_encode_pll(struct via_pll_config pll) argument 51 return (pll [all...] |
/drivers/bcma/ |
H A D | driver_chipcommon_pmu.c | 212 /* Find the output of the "m" pll divider given pll controls that start with 290 u32 pll; local 293 pll = BCMA_CC_PMU5356_MAINPLL_PLL0; 297 pll = BCMA_CC_PMU5357_MAINPLL_PLL0; 300 pll = BCMA_CC_PMU4716_MAINPLL_PLL0; 306 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
|
/drivers/char/ |
H A D | genrtc.c | 270 struct rtc_pll_info pll; local 276 if (get_rtc_pll(&pll)) 279 return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0; 284 if (copy_from_user(&pll, argp, sizeof(pll))) 286 return set_rtc_pll(&pll); 395 struct rtc_pll_info pll; local 445 if (!get_rtc_pll(&pll)) 453 pll [all...] |
/drivers/cpufreq/ |
H A D | cpufreq-nforce2.c | 63 * @pll: PLL value 67 static int nforce2_calc_fsb(int pll) argument 71 mul = (pll >> 8) & 0xff; 72 div = pll & 0xff; 112 * @pll: PLL value 116 static void nforce2_write_pll(int pll) argument 120 /* Set the pll addr. to 0x00 */ 125 pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll); 174 int pll = 0; local 190 pll [all...] |
/drivers/media/common/tuners/ |
H A D | tda18271-common.c | 248 enum tda18271_pll pll, int force) 253 int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4; 397 /* main pll cp source on */ 401 /* main pll cp source off */ 405 msleep(5); /* pll locking */ 417 msleep(5); /* pll locking */ 432 msleep(5); /* pll locking */ 444 msleep(5); /* pll locking */ 460 msleep(5); /* pll locking */ 471 msleep(5); /* pll lockin 247 tda18271_charge_pump_source(struct dvb_frontend *fe, enum tda18271_pll pll, int force) argument [all...] |
/drivers/media/radio/ |
H A D | tef6862.c | 108 u16 pll; local 115 pll = 1964 + ((f->frequency - TEF6862_LO_FREQ) * 20) / FREQ_MUL; 117 i2cmsg[1] = (pll >> 8) & 0xff; 118 i2cmsg[2] = pll & 0xff;
|
/drivers/net/wireless/ath/ath9k/ |
H A D | ar9002_phy.c | 455 u32 pll; local 466 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); 467 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); 470 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 472 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 474 return pll;
|
/drivers/video/aty/ |
H A D | mach64_ct.c | 17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll); 18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll); 19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll); 20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll); 119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) argument 126 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; 127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; 129 ras_multiplier = pll 208 aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) argument 250 aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument 263 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) argument 280 aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) argument 376 aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll) argument 400 aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) argument 606 aty_resume_pll_ct(const struct fb_info *info, union aty_pll *pll) argument [all...] |
/drivers/video/matrox/ |
H A D | g450_pll.c | 35 return (minfo->features.pll.ref_freq * n + (m >> 1)) / m; 99 n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2; 137 unsigned int mnp, unsigned int pll) 139 switch (pll) { 174 unsigned int mnp, unsigned int pll) 180 switch (pll) { 230 unsigned int pll) 232 return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll)); 235 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { argument 136 g450_setpll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 173 g450_cmppll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 229 g450_testpll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 245 matroxfb_g450_setpll_cond(struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 253 g450_findworkingpll(struct matrox_fb_info *minfo, unsigned int pll, unsigned int *mnparray, unsigned int mnpcount) argument 331 __g450_setclk(struct matrox_fb_info *minfo, unsigned int fout, unsigned int pll, unsigned int *mnparray, unsigned int *deltaarray) argument 516 matroxfb_g450_setclk(struct matrox_fb_info *minfo, unsigned int fout, unsigned int pll) argument [all...] |
H A D | matroxfb_misc.c | 128 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, argument 132 unsigned int fxtal = pll->ref_freq; 141 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); 142 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); 144 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); 145 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); 146 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); 147 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); 148 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); 151 for (p = 1; p <= pll [all...] |
/drivers/media/dvb/frontends/ |
H A D | dib8000.h | 14 struct dibx000_bandwidth_config *pll; member in struct:dib8000_config 61 struct dibx000_bandwidth_config *pll); 150 struct dibx000_bandwidth_config *pll) 149 dib8000_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *pll) argument
|
/drivers/video/ |
H A D | svgalib.c | 381 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) argument 388 ar = pll->r_max; 398 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { 404 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) 412 am = pll->m_min; 413 an = pll->n_min; 415 while ((am <= pll->m_max) && (an <= pll [all...] |
/drivers/gpu/drm/radeon/ |
H A D | atombios_crtc.c | 508 struct radeon_pll *pll, 523 /* reset the pll flags */ 524 pll->flags = 0; 530 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 534 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 536 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 539 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 541 pll->flags |= RADEON_PLL_LEGACY; 544 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 546 pll 506 atombios_adjust_pll(struct drm_crtc *crtc, struct drm_display_mode *mode, struct radeon_pll *pll, bool ss_enabled, struct radeon_atom_ss *ss) argument 883 struct radeon_pll *pll; local [all...] |
H A D | radeon_legacy_crtc.c | 715 struct radeon_pll *pll; local 738 pll = &rdev->clock.p2pll; 740 pll = &rdev->clock.p1pll; 742 pll->flags = RADEON_PLL_LEGACY; 745 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 747 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 759 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 774 pll->flags |= RADEON_PLL_USE_REF_DIV; 782 radeon_compute_pll_legacy(pll, mode->clock, 813 pll_gain = radeon_compute_pll_gain(pll [all...] |
/drivers/media/dvb/bt8xx/ |
H A D | dvb-bt8xx.c | 202 u32 band, pll; local 224 /* compute the pll divider needed, from Conexant data sheet, 231 pll=0xf8000000| 243 cx24110_pll_write(fe,pll);
|
/drivers/media/video/cx88/ |
H A D | cx88-core.c | 774 u64 pll; local 783 pll = ofreq * 8 * prescale * (u64)(1 << 20); 784 do_div(pll,xtal); 785 reg = (pll & 0x3ffffff) | (pre[prescale] << 26); 787 printk("%s/0: pll out of range\n",core->name); 797 dprintk(1,"pll locked [pre=%d,ofreq=%d]\n", 801 dprintk(1,"pll not locked yet, waiting ...\n"); 804 dprintk(1,"pll NOT locked [pre=%d,ofreq=%d]\n",prescale,ofreq);
|