/drivers/gpu/drm/nouveau/ |
H A D | nv04_cursor.c | 34 crtcstate->CRTC[index]); 45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = 48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = 51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= 53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
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H A D | nv04_crtc.c | 46 crtcstate->CRTC[index]); 55 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 57 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 58 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode, 334 * CRTC 336 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 337 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 338 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 339 regp->CRTC[NV_CIO_CR_HBE_INDE [all...] |
H A D | nv04_tv.c | 103 state->CRTC[NV_CIO_CRE_49] |= 0x10; 105 state->CRTC[NV_CIO_CRE_49] &= ~0x10; 108 state->CRTC[NV_CIO_CRE_LCD__INDEX]); 110 state->CRTC[NV_CIO_CRE_49]); 144 * they might be useful if we ever allow a CRTC to drive 165 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
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H A D | nouveau_hw.h | 128 NV_REG_DEBUG(CRTC, dev, "head %d reg %08x val %08x\n", head, reg, val); 137 NV_REG_DEBUG(CRTC, dev, "head %d reg %08x val %08x\n", head, reg, val); 411 * for changes to the CRTC CURCTL regs to take effect, whether changing 442 &dev_priv->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
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H A D | nv04_dfp.c | 107 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= 252 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; 253 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; 295 NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index); 298 /* Initialize the FP registers in this CRTC. */ 479 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
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H A D | nv17_tv.c | 397 uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[ 463 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ 464 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ 595 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
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H A D | nouveau_hw.c | 638 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); 645 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
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H A D | nouveau_drv.h | 613 uint8_t CRTC[0xa0]; member in struct:nv04_crtc_reg
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/drivers/video/matrox/ |
H A D | matroxfb_misc.c | 205 /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */ 303 hw->CRTC[0] = ht-4; 304 hw->CRTC[1] = hd; 305 hw->CRTC[2] = hd; 306 hw->CRTC[3] = (hbe & 0x1F) | 0x80; 307 hw->CRTC[4] = hs; 308 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F); 309 hw->CRTC[6] = vt & 0xFF; 310 hw->CRTC[7] = ((vt & 0x100) >> 8) | 318 hw->CRTC[ [all...] |
H A D | matroxfb_base.c | 326 p0 = minfo->hw.CRTC[0x0D] = pos & 0xFF; 327 p1 = minfo->hw.CRTC[0x0C] = (pos & 0xFF00) >> 8; 820 hw->CRTC[0x0D] = pos & 0xFF; 821 hw->CRTC[0x0C] = (pos & 0xFF00) >> 8; 2534 MODULE_PARM_DESC(outputs, "Specifies which CRTC is mapped to which output (string of up to three letters, consisting of 0 (disabled), 1 (CRTC1), 2 (CRTC2)) (default=111 for Gx50, 101 for G200/G400 with DFP, and 100 for all other devices)");
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H A D | matroxfb_base.h | 222 unsigned int delay; /* CRTC delay */ 290 unsigned char CRTC[25]; member in struct:matrox_hw_state
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/drivers/video/ |
H A D | neofb.c | 288 * CRTC Controller 290 par->CRTC[0] = htotal - 5; 291 par->CRTC[1] = (var->xres >> 3) - 1; 292 par->CRTC[2] = (var->xres >> 3) - 1; 293 par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80; 294 par->CRTC[4] = ((var->xres + var->right_margin) >> 3); 295 par->CRTC[5] = (((htotal - 1) & 0x20) << 2) 297 par->CRTC[6] = (vtotal - 2) & 0xFF; 298 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8) 305 par->CRTC[ [all...] |
/drivers/usb/misc/sisusbvga/ |
H A D | sisusb_struct.h | 73 unsigned char CRTC[0x19]; member in struct:SiS_StandTable
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H A D | sisusb_init.c | 378 /* CRTC */ 390 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; 508 /* CRTC/2 */
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/drivers/video/savage/ |
H A D | savagefb_driver.c | 131 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or 132 CRTC[17] */ 133 VGAwCR(17, reg->CRTC[17] & ~0x80, par); 136 VGAwCR(i, reg->CRTC[i], par); 172 * CRTC Controller 174 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; 175 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; 176 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; 177 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; 178 reg->CRTC[ [all...] |
H A D | savagefb.h | 155 unsigned char CRTC[25]; /* Crtc Controller */ member in struct:savage_reg
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/drivers/staging/xgifb/ |
H A D | vb_struct.h | 57 unsigned char CRTC[0x19]; member in struct:XGI_StandTableStruct
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H A D | vb_setmode.c | 240 xgifb_reg_set(pVBInfo->P3d4, 0x11, CRTCdata); /* Unlock CRTC */ 243 /* Get CRTC from file */ 244 CRTCdata = pVBInfo->StandTable[StandTableIndex].CRTC[i]; 245 xgifb_reg_set(pVBInfo->P3d4, i, CRTCdata); /* Set CRTC(3d4) */ 609 xgifb_reg_set(pVBInfo->P3d4, 0x11, data); /* Unlock CRTC */ 629 /* Input : Stand or enhance CRTC table */ 643 Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[4]; 647 Tempbx = pVBInfo->StandTable[StandTableIndex].CRTC[5]; 660 Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[16]; 666 Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[ [all...] |
/drivers/video/sis/ |
H A D | vstruct.h | 136 unsigned char CRTC[0x19]; member in struct:SiS_StandTable_S
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H A D | init.c | 1721 /* HELPER: OPEN/CLOSE CRT1 CRTC */ 1744 #if 0 /* This locks some CRTC registers. We don't want that. */ 1881 /* CRTC */ 1890 /* Unlock CRTC */ 1894 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; 1901 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; 2068 /* CRTC/2 */ 3638 /* Terrible hack, but correct CRTC data for
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H A D | init301.c | 3025 tempax = SiS_Pr->SiS_StandTable[index].CRTC[0]; 3026 tempbx = SiS_Pr->SiS_StandTable[index].CRTC[6]; 3027 temp1 = SiS_Pr->SiS_StandTable[index].CRTC[7];
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