Searched refs:idx_value (Results 1 - 6 of 6) sorted by relevance

/drivers/gpu/drm/radeon/
H A Dr200.c155 u32 idx_value; local
159 idx_value = radeon_get_ib_value(p, idx);
187 track->zb.offset = idx_value;
189 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
200 track->cb[0].offset = idx_value;
202 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
218 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
261 track->textures[i].cube_info[face - 1].offset = idx_value;
262 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
267 track->maxy = ((idx_value >> 1
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H A Dr300.c629 u32 idx_value; local
633 idx_value = radeon_get_ib_value(p, idx);
665 track->cb[i].offset = idx_value;
667 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
678 track->zb.offset = idx_value;
680 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
708 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
709 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
718 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
728 track->vap_vf_cntl = idx_value;
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H A Dr100.c119 u32 idx_value; local
139 idx_value = radeon_get_ib_value(p, idx);
142 track->arrays[i + 0].esize = idx_value >> 8;
154 track->arrays[i + 1].esize = idx_value >> 24;
165 idx_value = radeon_get_ib_value(p, idx);
168 track->arrays[i + 0].esize = idx_value >> 8;
1493 u32 idx_value; local
1498 idx_value = radeon_get_ib_value(p, idx);
1527 track->zb.offset = idx_value;
1529 ib[idx] = idx_value
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H A Devergreen_cs.c1027 u32 idx_value; local
1032 idx_value = radeon_get_ib_value(p, idx);
1062 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1100 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1118 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1136 ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1220 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1233 if (idx_value & 0x10) {
1301 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
1317 start_reg = (idx_value <<
1697 u32 idx_value = ib[idx]; local
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H A Dr600_cs.c1411 u32 idx_value; local
1416 idx_value = radeon_get_ib_value(p, idx);
1446 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1480 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1517 if (idx_value & 0x10) {
1572 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1588 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1608 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1682 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1693 start_reg = (idx_value <<
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H A Dradeon_ring.c43 u32 idx_value = 0; local
60 idx_value = ibc->kpage[new_page][pg_offset/4];
61 return idx_value;

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