Searched refs:mode2 (Results 1 - 13 of 13) sorted by relevance

/drivers/gpu/drm/
H A Ddrm_modes.c749 * @mode2: second mode
754 * Check to see if @mode1 and @mode2 are equivalent.
759 bool drm_mode_equal(struct drm_display_mode *mode1, struct drm_display_mode *mode2) argument
763 if (mode1->clock && mode2->clock) {
764 if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock))
766 } else if (mode1->clock != mode2->clock)
769 if (mode1->hdisplay == mode2->hdisplay &&
770 mode1->hsync_start == mode2->hsync_start &&
771 mode1->hsync_end == mode2->hsync_end &&
772 mode1->htotal == mode2
[all...]
/drivers/video/
H A Dmodedb.c841 * @mode2: second videomode
847 const struct fb_videomode *mode2)
849 return (mode1->xres == mode2->xres &&
850 mode1->yres == mode2->yres &&
851 mode1->pixclock == mode2->pixclock &&
852 mode1->hsync_len == mode2->hsync_len &&
853 mode1->vsync_len == mode2->vsync_len &&
854 mode1->left_margin == mode2->left_margin &&
855 mode1->right_margin == mode2->right_margin &&
856 mode1->upper_margin == mode2
846 fb_mode_is_equal(const struct fb_videomode *mode1, const struct fb_videomode *mode2) argument
[all...]
H A Dsh_mobile_hdmi.c1053 struct fb_videomode mode1, mode2; local
1056 fb_var_to_videomode(&mode2, new_var);
1059 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1061 if (fb_mode_is_equal(&mode1, &mode2)) {
1069 mode1.yres, mode2.yres);
H A Dfbmem.c943 struct fb_videomode mode1, mode2; local
946 fb_var_to_videomode(&mode2, &info->var);
948 ret = fb_mode_is_equal(&mode1, &mode2);
H A Dsh_mobile_lcdcfb.c1043 struct fb_videomode mode1, mode2; local
1052 fb_var_to_videomode(&mode2, &info->var);
1054 if (fb_mode_is_equal(&mode1, &mode2))
/drivers/tty/serial/
H A Dsb1250-duart.c264 unsigned int clr = 0, set = 0, mode2; local
277 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
278 mode2 &= ~M_DUART_CHAN_MODE;
280 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
282 mode2 |= V_DUART_CHAN_MODE_NORMAL;
286 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
545 unsigned int mode1 = 0, mode2 = 0, aux = 0; local
574 mode2 |= M_DUART_STOP_BIT_LEN_2;
576 mode2 |= M_DUART_STOP_BIT_LEN_1;
637 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode
[all...]
/drivers/ide/
H A Dpalm_bk3710.c169 u8 mode2 = mate->pio_mode - XFER_PIO_0; local
171 if (mode2 < mode)
172 mode = mode2;
/drivers/gpu/drm/radeon/
H A Drs690.c172 struct drm_display_mode *mode2)
193 if (mode1 && mode2) {
194 if (mode1->hdisplay > mode2->hdisplay) {
199 } else if (mode2->hdisplay > mode1->hdisplay) {
200 if (mode2->hdisplay > 2560)
208 } else if (mode2) {
170 rs690_line_buffer_adjust(struct radeon_device *rdev, struct drm_display_mode *mode1, struct drm_display_mode *mode2) argument
H A Dr100.c2854 struct drm_display_mode *mode2 = NULL; local
2866 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2878 if (mode2)
2905 if (mode2) {
2907 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3127 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3175 if (mode2) {
3177 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
H A Dradeon_asic.h253 struct drm_display_mode *mode2);
/drivers/media/video/
H A Dmt9p031.c125 u16 mode2; member in struct:mt9p031
161 u16 value = (mt9p031->mode2 & ~clear) | set;
168 mt9p031->mode2 = value;
857 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC;
/drivers/staging/comedi/drivers/
H A Dni_mio_common.c2386 int mode2 = 0; local
2433 mode2 &= ~AI_Pre_Trigger;
2434 mode2 &= ~AI_SC_Initial_Load_Source;
2435 mode2 &= ~AI_SC_Reload_Mode;
2436 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2511 mode2 |= AI_SI_Reload_Mode(0);
2513 mode2 &= ~AI_SI_Initial_Load_Source;
2514 /* mode2 |= AI_SC_Reload_Mode; */
2515 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2553 mode2
[all...]
/drivers/media/video/gspca/
H A Dgspca.c1184 int w, h, mode, mode2; local
1201 mode2 = gspca_get_mode(gspca_dev, mode,
1203 if (mode2 >= 0)
1204 mode = mode2;

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