/drivers/net/wan/ |
H A D | cycx_x25.c | 252 cfg.clock = conf->clocking == WANOPT_EXTERNAL ? 8 : 55; 1085 the clock to external */ 1089 x25_cmd_conf.conf[1].clock = 8; 1551 pr_info("clock=%sternal\n", conf->clock == 8 ? "Ex" : "In");
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/drivers/cpufreq/ |
H A D | s5pv210-cpufreq.c | 24 #include <mach/regs-clock.h> 265 /* Check if there need to change System bus clock */ 272 * temporary clock while changing divider. 273 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 286 * Some clock source's clock API are not prepared. 287 * Do not use clock API in below code. 391 * 7. Change souce clock from SCLKMPLL(667Mhz) 440 * L4 level need to change memory bus speed, hence onedram clock divier
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/drivers/gpu/drm/i2c/ |
H A D | ch7006_drv.c | 232 for (mode = ch7006_modes; mode->mode.clock; mode++) {
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/drivers/gpu/drm/i915/ |
H A D | intel_bios.h | 299 u16 clock; /**< In 10khz */ member in struct:lvds_dvo_timing
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H A D | intel_drv.h | 117 mode->clock *= multiplier;
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/drivers/mmc/host/ |
H A D | sdhci.h | 263 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
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H A D | jz4740_mmc.c | 619 if (ios->clock) 620 jz4740_mmc_set_clock_rate(host, ios->clock); 833 dev_err(&pdev->dev, "Failed to get mmc clock\n");
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H A D | mxs-mmc.c | 594 "%s: cannot set clock to %d\n", __func__, rate); 624 if (ios->clock) 625 mxs_mmc_set_clk_rate(host, ios->clock);
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H A D | vub300.c | 1979 if (ios->clock >= 48000000) 1981 else if (ios->clock >= 24000000) 1983 else if (ios->clock >= 20000000) 1985 else if (ios->clock >= 15000000) 1987 else if (ios->clock >= 200000)
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H A D | omap.c | 270 /* Keeps clock running for at least 8 cycles on valid freq */ 1214 if (ios->clock == 0) 1217 dsor = func_clk_rate / ios->clock; 1221 if (func_clk_rate / dsor > ios->clock) 1283 /* Send clock cycles, poll completion */
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/drivers/net/can/sja1000/ |
H A D | plx_pci.c | 95 * You will probably also want to set the clock divider value to 7 149 u8 cdr; /* clock divider register */ 548 priv->can.clock.freq = ci->can_clock;
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/drivers/scsi/ |
H A D | 53c700.h | 196 int clock; /* board clock speed in MHz */ member in struct:NCR_700_Host_Parameters 212 __u32 fast:1; /* if we can alter the SCSI bus clock
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H A D | nsp32.h | 593 int clock; /* clock dividing flag */ member in struct:_nsp32_hw_data 594 nsp32_sync_table *synct; /* sync_table determined by clock */
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H A D | qlogicpti.h | 368 char differential, ultra, clock; member in struct:qlogicpti
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/drivers/tty/ |
H A D | moxa.c | 1733 unsigned int clock, val; local 1741 clock = 921600; 1742 val = clock / baud; 1744 baud = clock / val;
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/drivers/video/aty/ |
H A D | radeonfb.h | 257 int clock; member in struct:panel_info
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/drivers/video/savage/ |
H A D | savagefb.h | 210 int clock[4]; member in struct:savagefb_par
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H A D | savagefb_driver.c | 37 * - clock validations in decode_var 1027 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ 1029 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ 1034 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ 1036 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ 1041 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ 1043 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ 1517 par->dacSpeedBpp = par->clock[3]; 1519 par->dacSpeedBpp = par->clock[2]; 1521 par->dacSpeedBpp = par->clock[ [all...] |
/drivers/gpu/drm/gma500/ |
H A D | mdfld_dsi_dpi.c | 445 * byte clock counts were calculated by following formula 510 /*max value: 20 clock cycles of txclkesc*/ 704 adjusted_mode->clock = fixed_mode->clock; 849 * configure. This also starts the DSI clock at 200MHz. 854 /* Now start the DSI clock */
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/drivers/gpu/drm/radeon/ |
H A D | radeon_i2c.c | 199 static void set_clock(void *i2c_priv, int clock) argument 208 val |= clock ? 0 : rec->en_clk_mask; 1155 /* clock/data router switching */
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H A D | radeon_legacy_encoders.c | 196 radeon_encoder->pixel_clock = adjusted_mode->clock; 766 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { 917 radeon_encoder->pixel_clock = adjusted_mode->clock; 941 /*if (mode->clock > 165000)
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/drivers/input/keyboard/ |
H A D | lm8323.c | 55 #define LM8323_CMD_WRITE_CLOCK 0x93 /* Set clock config. */ 56 #define LM8323_CMD_READ_CLOCK 0x94 /* Get clock config. */ 87 #define CLK_SLOWCLKEN 0x08 /* Enable 32.768kHz clock. */ 110 * Ramp. If s is 1, divide clock by 512, else divide clock by 16. 111 * Take t clock scales (up to 63) per step, for n steps (up to 126). 336 int clock = (CLK_SLOWCLKEN | CLK_RCPWM_EXTERNAL); local 348 lm8323_write(lm, 2, LM8323_CMD_WRITE_CLOCK, clock);
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/drivers/media/dvb/pt1/ |
H A D | pt1.c | 882 int clock, int data, int next_addr) 885 !clock << 11 | !data << 10 | next_addr); 881 pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable, int clock, int data, int next_addr) argument
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/drivers/misc/ |
H A D | Kconfig | 86 TC block with a 5+ MHz base clock rate. Two timer channels 90 may be used as a clock event device supporting oneshot mode 91 (delays of up to two seconds) based on the 32 KiHz clock. 101 choice of which one to use for the clock framework. The other 197 ICS932S401 clock control chips. 265 This driver provides a clock event source based on the MFGPT
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/drivers/usb/host/ |
H A D | oxu210hp-hcd.c | 2253 unsigned frame, clock, now_uframe, mod; local 2265 clock = readl(&oxu->regs->frame_index); 2267 clock = now_uframe + mod - 1; 2268 clock %= mod; 2277 if (frame == (clock >> 3)) 2331 if (now_uframe == clock) { 2342 clock = now;
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