/arch/sh/include/asm/ |
H A D | bitops-grb.h | 6 int mask; local 11 mask = 1 << (nr & 0x1f); 24 : "r" (mask) 30 int mask; local 35 mask = ~(1 << (nr & 0x1f)); 47 : "r" (mask) 53 int mask; local 58 mask = 1 << (nr & 0x1f); 70 : "r" (mask) 76 int mask, retva local 107 int mask, retval,not_mask; local 141 int mask, retval; local [all...] |
H A D | bitops-llsc.h | 6 int mask; local 11 mask = 1 << (nr & 0x1f); 20 : "r" (a), "r" (mask) 27 int mask; local 32 mask = 1 << (nr & 0x1f); 41 : "r" (a), "r" (~mask) 48 int mask; local 53 mask = 1 << (nr & 0x1f); 62 : "r" (a), "r" (mask) 69 int mask, retva local 94 int mask, retval; local 120 int mask, retval; local [all...] |
H A D | bitops-op32.h | 30 unsigned long mask = BIT_MASK(nr); local 33 *p |= mask; 48 unsigned long mask = BIT_MASK(nr); local 51 *p &= ~mask; 75 unsigned long mask = BIT_MASK(nr); local 78 *p ^= mask; 93 unsigned long mask = BIT_MASK(nr); local 97 *p = old | mask; 98 return (old & mask) != 0; 112 unsigned long mask local 124 unsigned long mask = BIT_MASK(nr); local [all...] |
/arch/arm/mach-bcmring/include/csp/ |
H A D | intcHw.h | 36 static inline void intcHw_irq_disable(void *basep, uint32_t mask); 37 static inline void intcHw_irq_enable(void *basep, uint32_t mask);
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/arch/arm/mach-sa1100/include/mach/ |
H A D | reset.h | 13 static inline void clear_reset_status(unsigned int mask) argument 15 RCSR = mask;
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/arch/sparc/include/asm/ |
H A D | bitops_32.h | 21 extern unsigned long ___set_bit(unsigned long *addr, unsigned long mask); 22 extern unsigned long ___clear_bit(unsigned long *addr, unsigned long mask); 23 extern unsigned long ___change_bit(unsigned long *addr, unsigned long mask); 33 unsigned long *ADDR, mask; local 36 mask = 1 << (nr & 31); 38 return ___set_bit(ADDR, mask) != 0; 43 unsigned long *ADDR, mask; local 46 mask = 1 << (nr & 31); 48 (void) ___set_bit(ADDR, mask); 53 unsigned long *ADDR, mask; local 63 unsigned long *ADDR, mask; local 73 unsigned long *ADDR, mask; local 83 unsigned long *ADDR, mask; local [all...] |
/arch/arm/mach-bcmring/include/mach/csp/ |
H A D | secHw_inline.h | 35 static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ 39 if (mask & 0x0000FFFF) { 40 regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; 43 if (mask & 0xFFFF0000) { 44 regp->reg[secHw_IDX_MS].setSecure = mask >> 16; 54 static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ 58 if (mask & 0x0000FFFF) { 59 regp->reg[secHw_IDX_LS].setUnsecure = mask [all...] |
/arch/x86/include/asm/ |
H A D | word-at-a-time.h | 6 * optimal byte mask counting is probably going to be something 16 * the simpler "(mask & ONEBYTES) * ONEBYTES >> 56" 18 * mask them first. 20 static inline long count_masked_bytes(unsigned long mask) argument 22 return mask*0x0001020304050608ul >> 56; 28 static inline long count_masked_bytes(long mask) argument 31 long a = (0x0ff0001+mask) >> 23; 33 return a & mask;
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H A D | mpspec.h | 111 unsigned long mask[PHYSID_ARRAY_SIZE]; member in struct:physid_mask 116 #define physid_set(physid, map) set_bit(physid, (map).mask) 117 #define physid_clear(physid, map) clear_bit(physid, (map).mask) 118 #define physid_isset(physid, map) test_bit(physid, (map).mask) 120 test_and_set_bit(physid, (map).mask) 123 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) 126 bitmap_or((dst).mask, (src1).mask, (src [all...] |
/arch/m32r/include/asm/ |
H A D | smp.h | 16 unsigned long mask[PHYSID_ARRAY_SIZE]; member in struct:physid_mask 21 #define physid_set(physid, map) set_bit(physid, (map).mask) 22 #define physid_clear(physid, map) clear_bit(physid, (map).mask) 23 #define physid_isset(physid, map) test_bit(physid, (map).mask) 24 #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask) 26 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) 27 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src [all...] |
/arch/powerpc/math-emu/ |
H A D | mtfsf.c | 11 u32 mask; local 18 mask = 0x9fffffff; 20 mask = 0; 22 mask |= 0x90000000; 24 mask |= 0x0f000000; 26 mask |= 0x00f00000; 28 mask |= 0x000f0000; 30 mask |= 0x0000f000; 32 mask |= 0x00000f00; 34 mask | [all...] |
/arch/arm/plat-samsung/ |
H A D | wakeup-mask.c | 1 /* arch/arm/plat-samsung/wakeup-mask.c 5 * Support for wakeup mask interrupts on newer SoCs 19 #include <plat/wakeup-mask.h> 23 struct samsung_wakeup_mask *mask, int nr_mask) 30 for (; nr_mask > 0; nr_mask--, mask++) { 31 if (mask->irq == NO_WAKEUP_IRQ) { 32 val |= mask->bit; 36 data = irq_get_irq_data(mask->irq); 40 val &= ~mask->bit; 42 val |= mask 22 samsung_sync_wakemask(void __iomem *reg, struct samsung_wakeup_mask *mask, int nr_mask) argument [all...] |
/arch/mips/bcm63xx/ |
H A D | prom.c | 20 u32 reg, mask; local 30 mask = CKCTL_6338_ALL_SAFE_EN; 32 mask = CKCTL_6345_ALL_SAFE_EN; 34 mask = CKCTL_6348_ALL_SAFE_EN; 36 mask = CKCTL_6358_ALL_SAFE_EN; 38 mask = CKCTL_6368_ALL_SAFE_EN; 40 mask = 0; 43 reg &= ~mask;
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/arch/powerpc/sysdev/ |
H A D | mpc8xx_pic.h | 11 * Some internal interrupt registers use an 8-bit mask for the interrupt 14 static inline uint mk_int_int_mask(uint mask) argument 16 return (1 << (7 - (mask/2)));
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/arch/sh/include/mach-common/mach/ |
H A D | magicpanelr2.h | 22 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) 23 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) 24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) 25 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) 26 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, re [all...] |
H A D | secureedge5410.h | 43 #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ 45 ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
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/arch/tile/include/asm/ |
H A D | bitops_32.h | 22 unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask); 23 unsigned long _atomic_andn(volatile unsigned long *p, unsigned long mask); 24 unsigned long _atomic_xor(volatile unsigned long *p, unsigned long mask); 85 unsigned long mask = BIT_MASK(nr); local 88 return (_atomic_or(addr, mask) & mask) != 0; 101 unsigned long mask = BIT_MASK(nr); local 104 return (_atomic_andn(addr, mask) & mask) != 0; 118 unsigned long mask local [all...] |
H A D | bitops_64.h | 25 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); local 26 __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask); 31 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); local 32 __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask); 41 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); local 48 guess, guess ^ mask); 63 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); local 65 val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask) 66 & mask) != 0; 75 unsigned long mask local 87 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); local [all...] |
/arch/arm/mach-msm/ |
H A D | sirc.c | 43 /* Mask off the given interrupt. Keep the int_enable mask in sync with 47 unsigned int mask; local 49 mask = 1 << (d->irq - FIRST_SIRC_IRQ); 50 writel(mask, sirc_regs.int_enable_clear); 51 int_enable &= ~mask; 55 /* Unmask the given interrupt. Keep the int_enable mask in sync with 59 unsigned int mask; local 61 mask = 1 << (d->irq - FIRST_SIRC_IRQ); 62 writel(mask, sirc_regs.int_enable_set); 63 int_enable |= mask; 69 unsigned int mask; local 78 unsigned int mask; local 92 unsigned int mask; local [all...] |
/arch/frv/include/asm/ |
H A D | bitops.h | 36 unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v) argument 51 : "NPr"(~mask) 59 unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v) argument 74 : "NPr"(mask) 82 unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v) argument 97 : "NPr"(mask) 106 extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v); 107 extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v); 108 extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v); 112 #define atomic_clear_mask(mask, 118 unsigned long mask = 1UL << (nr & 31); local 126 unsigned long mask = 1UL << (nr & 31); local 134 unsigned long mask = 1UL << (nr & 31); local 157 int mask; local 167 int mask; local 177 int mask; local 187 int mask, retval; local 199 int mask, retval; local 211 int mask, retval; local 232 int mask; local [all...] |
/arch/arm/mach-rpc/ |
H A D | irq.c | 12 unsigned int val, mask; local 14 mask = 1 << d->irq; 16 iomd_writeb(val & ~mask, IOMD_IRQMASKA); 17 iomd_writeb(mask, IOMD_IRQCLRA); 22 unsigned int val, mask; local 24 mask = 1 << d->irq; 26 iomd_writeb(val & ~mask, IOMD_IRQMASKA); 31 unsigned int val, mask; local 33 mask = 1 << d->irq; 35 iomd_writeb(val | mask, IOMD_IRQMASK 46 unsigned int val, mask; local 55 unsigned int val, mask; local 70 unsigned int val, mask; local 79 unsigned int val, mask; local 94 unsigned int val, mask; local 103 unsigned int val, mask; local [all...] |
/arch/arm/mach-lpc32xx/ |
H A D | irq.c | 70 u32 mask; member in struct:lpc32xx_event_info 74 * Maps an IRQ number to and event mask and register 79 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT, 83 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT, 87 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT, 91 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT, 95 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT, 99 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT, 103 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT, 107 .mask 204 unsigned int reg, ctrl, mask; local 214 unsigned int reg, ctrl, mask; local 224 unsigned int ctrl, mask; local 239 unsigned int reg, ctrl, mask; local [all...] |
/arch/mips/include/asm/pmc-sierra/msp71xx/ |
H A D | msp_regops.h | 72 u32 const mask, 88 : "ir" (~mask), "ir" (value), "m" (*addr)); 95 u32 const mask) 109 : "ir" (mask), "m" (*addr)); 116 u32 const mask) 130 : "ir" (~mask), "m" (*addr)); 137 u32 const mask) 151 : "ir" (mask), "m" (*addr)); 158 u32 const mask) 166 " and %0, %2 # mask \ 71 set_value_reg32(volatile u32 *const addr, u32 const mask, u32 const value) argument 94 set_reg32(volatile u32 *const addr, u32 const mask) argument 115 clear_reg32(volatile u32 *const addr, u32 const mask) argument 136 toggle_reg32(volatile u32 *const addr, u32 const mask) argument 157 read_reg32(volatile u32 *const addr, u32 const mask) argument [all...] |
/arch/cris/include/asm/ |
H A D | bitops.h | 74 unsigned int mask, retval; local 79 mask = 1 << (nr & 0x1f); 81 retval = (mask & *adr) != 0; 82 *adr |= mask; 104 unsigned int mask, retval; local 109 mask = 1 << (nr & 0x1f); 111 retval = (mask & *adr) != 0; 112 *adr &= ~mask; 128 unsigned int mask, retval; local 132 mask [all...] |
/arch/ia64/include/asm/sn/ |
H A D | leds.h | 26 set_led_bits(u8 value, u8 mask) argument 28 pda->led_state = (pda->led_state & ~mask) | (value & mask);
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