Searched refs:ADDR (Results 1 - 14 of 14) sorted by relevance

/drivers/net/fddi/skfp/
H A Dhwt.c81 outpd(ADDR(B2_TI_INI), (u_long) cnt * 200) ; /* Load timer value. */
82 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */
103 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
104 outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ;
171 tr = (u_short)((inpd(ADDR(B2_TI_VAL))/200) & 0xffff) ;
204 interval = inpd(ADDR(B2_TI_INI)) ;
205 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
206 time = inpd(ADDR(B2_TI_VAL)) ;
207 outpd(ADDR(B2_TI_INI),time) ;
208 outpw(ADDR(B2_TI_CRT
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H A Ddrvfbi.c103 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ;
108 outp(ADDR(B0_CTRL),CTRL_RST_SET) ; /* reset for all chips */
109 i = (int) inp(ADDR(B0_CTRL)) ; /* do dummy read */
111 outp(ADDR(B0_CTRL), CTRL_RST_CLR) ;
116 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_ON) ; /* enable for writes */
119 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_OFF) ; /* disable writes */
126 outp(ADDR(B0_CTRL), CTRL_MRST_CLR|CTRL_HPI_CLR) ;
145 outpd(ADDR(B4_R1_F), RX_WATERMARK) ;
146 outpd(ADDR(B5_XA_F), TX_WATERMARK) ;
147 outpd(ADDR(B5_XS_
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H A Dfplustm.c56 #define DUMMY_READ() smc->hw.mc_dummy = (u_short) inp(ADDR(B0_RAP))
283 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R1_CSR) ;
284 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R1_DA) ;
290 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R2_CSR) ;
291 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R2_DA) ;
313 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XS_CSR) ;
314 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XS_DA) ;
324 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ;
325 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XA_DA) ;
871 smc->hw.fp.fm_st1u = (HW_PTR) ADDR(B0_ST1
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H A Dhwmtm.c376 outpd(ADDR(B5_XA_DA),phys) ;
389 outpd(ADDR(B5_XS_DA),phys) ;
411 outpd(ADDR(B4_R1_DA),phys) ;
568 outpd(ADDR(B5_XA_DA),phys) ;
570 outpd(ADDR(B0_XA_CSR),CSR_START) ;
573 outpd(ADDR(B5_XS_DA),phys) ;
575 outpd(ADDR(B0_XS_CSR),CSR_START) ;
582 outpd(ADDR(B4_R1_DA),phys) ;
583 outpd(ADDR(B0_R1_CSR),CSR_START) ;
793 outpd(ADDR(B4_R1_CS
[all...]
H A Dskfddi.c94 #undef ADDR // undo Linux definition macro
617 if (inpd(ADDR(B0_IMSK)) == 0) {
/drivers/net/fddi/skfp/h/
H A Dtargetos.h44 #undef ADDR macro
54 #undef ADDR macro
56 #define ADDR(a) (smc->hw.iop+(a)) macro
58 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), (smc->hw.iop+( ((a)&0x7F) | ((a)>>7 ? 0x80:0)) )) : (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) macro
H A Dskfbi.h934 #define ADDR(a) (char far *) smc->hw.iop+(a) macro
937 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \ macro
948 #define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */
950 #define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */
960 #define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */
961 #define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */
962 #define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */
963 #define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */
970 #define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank)
977 #define ISR_A ADDR(B0_ISR
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/drivers/isdn/hardware/eicon/
H A Dmi_pc.h36 #define ADDR 4 macro
H A Dos_bri.c534 addrLo = Port + ADDR;
617 addrLo = Port + ADDR;
657 addrLo = Port + ADDR;
678 addrLo = Port + ADDR;
H A Dplatform.h358 #undef ADDR macro
H A Ds_bri.c56 addrLo = Port + ADDR;
/drivers/platform/x86/
H A Dcompal-laptop.c381 #define SIMPLE_MASKED_STORE_SHOW(NAME, ADDR, MASK) \
385 return sprintf(buf, "%d\n", ((ec_read_u8(ADDR) & MASK) != 0)); \
391 u8 old_val = ec_read_u8(ADDR); \
394 ec_write(ADDR, state ? (old_val | MASK) : (old_val & ~MASK)); \
/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic.h1291 #define NX_PCI_READ_32(ADDR) readl((ADDR))
1292 #define NX_PCI_WRITE_32(DATA, ADDR) writel(DATA, (ADDR))
/drivers/atm/
H A Dzatm.c1065 "error at 0x%08x\n",dev->number,zin(ADDR));
1068 "parity error at 0x%08x\n",dev->number,zin(ADDR));
1071 "error at 0x%08x\n",dev->number,zin(ADDR));

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