Searched refs:MODE_REG (Results 1 - 10 of 10) sorted by relevance

/drivers/input/keyboard/
H A Dspear-keyboard.c29 #define MODE_REG 0x00 /* 16 bit reg */ macro
113 writew(val, kbd->io_base + MODE_REG);
117 val = readw(kbd->io_base + MODE_REG);
119 writew(val, kbd->io_base + MODE_REG);
130 val = readw(kbd->io_base + MODE_REG);
132 writew(val, kbd->io_base + MODE_REG);
/drivers/scsi/
H A Ddtc.c370 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE);
392 NCR5380_write(MODE_REG, 0); /* Clear the operating mode */
420 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE);
446 NCR5380_write(MODE_REG, 0); /* Clear the operating mode */
H A Dpas16.c183 0x1c02, /* MODE_REG */
329 NCR5380_write( MODE_REG, 0x20 ); /* Is it really SCSI? */
330 if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */
332 NCR5380_write( MODE_REG, 0x00 ); /* it back. */
333 if( NCR5380_read( MODE_REG ) != 0x00 )
H A DNCR5380.c426 mr = NCR5380_read(MODE_REG);
883 NCR5380_write(MODE_REG, MR_BASE);
1200 if ((NCR5380_read(MODE_REG) & MR_DMA) && ((basr & BASR_END_DMA_TRANSFER) || !(basr & BASR_PHASE_MATCH))) {
1216 NCR5380_write(MODE_REG, MR_BASE);
1220 dprintk(NDEBUG_INTR, ("scsi : unknown interrupt, BASR 0x%X, MR 0x%X, SR 0x%x\n", basr, NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG)));
1328 NCR5380_write(MODE_REG, MR_ARBITRATE);
1338 NCR5380_write(MODE_REG, MR_BASE);
1356 NCR5380_write(MODE_REG, MR_BASE);
1368 NCR5380_write(MODE_REG, MR_BASE);
1396 NCR5380_write(MODE_REG, MR_BAS
[all...]
H A Dsun3_NCR5380.c521 mr = NCR5380_read(MODE_REG);
833 NCR5380_write(MODE_REG, MR_BASE);
1187 NCR5380_write(MODE_REG, MR_BASE);
1255 if ((NCR5380_read(MODE_REG) & MR_DMA_MODE) &&
1270 HOSTNO, basr, NCR5380_read(MODE_REG),
1284 NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG));
1390 NCR5380_write(MODE_REG, MR_ARBITRATE);
1405 NCR5380_write(MODE_REG, MR_BASE);
1418 NCR5380_write(MODE_REG, MR_BASE);
1435 NCR5380_write(MODE_REG, MR_BAS
[all...]
H A Datari_NCR5380.c573 mr = NCR5380_read(MODE_REG);
888 NCR5380_write(MODE_REG, MR_BASE);
1242 NCR5380_write(MODE_REG, MR_BASE);
1322 if ((NCR5380_read(MODE_REG) & MR_DMA_MODE) &&
1337 HOSTNO, basr, NCR5380_read(MODE_REG),
1346 NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG));
1445 NCR5380_write(MODE_REG, MR_ARBITRATE);
1459 NCR5380_write(MODE_REG, MR_BASE);
1473 NCR5380_write(MODE_REG, MR_BASE);
1490 NCR5380_write(MODE_REG, MR_BAS
[all...]
H A DNCR5380.h94 #define MODE_REG 2 macro
H A Dg_NCR5380.c641 NCR5380_write(MODE_REG, MR_BASE);
/drivers/atm/
H A Diphase.h483 #define MODE_REG 0x00 macro
H A Diphase.c1458 writew(0, iadev->reass_reg+MODE_REG);
1630 writew(R_ONLINE, iadev->reass_reg+MODE_REG);

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