| /drivers/gpu/drm/nouveau/ |
| H A D | nv50_calc.c | 31 int *N1, int *M1, int *N2, int *M2, int *P)
42 *N2 = pll_vals.N2;
30 nv50_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk, int *N1, int *M1, int *N2, int *M2, int *P) argument
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| H A D | nv40_pm.c | 53 int N2 = (coef & 0xff000000) >> 24; local
64 clk = clk * N2 / M2;
110 u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P)
128 if (N2 && M2) {
130 *N2 = coef.N2;
133 *N2 = 1;
146 int N1, N2, M1, M2, log2P; local
155 &N1, &M1, &N2, &M2, &log2P);
159 if (N2
109 nv40_calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P) argument
[all...] |
| H A D | nouveau_calc.c | 388 int M1, N1, M2, N2, log2P; local
421 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
422 if (N2 < minN2)
424 if (N2 > maxN2)
429 if (N2/M2 < 4 || N2/M2 > 10)
432 calcclk2 = calcclk1 * N2 / M2;
450 bestpv->N2 = N2;
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| H A D | nv50_crtc.c | 335 int ret, N1, M1, N2, M2, P; local
342 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
347 pclk, ret, N1, M1, N2, M2, P);
353 nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
356 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
361 pclk, ret, N1, N2, M1, P);
366 nv_wr32(dev, pll.reg + 8, N2);
368 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
373 pclk, ret, N1, N2, M1, P);
377 nv_wr32(dev, pll.reg + 0x10, N2 << 1
[all...] |
| H A D | nouveau_hw.c | 227 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
233 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
234 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
313 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
403 pllvals->N2 = pllvals->M2 = 1;
418 pllvals->N2 = ((pll1 >> 21) & 0x18) |
477 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
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| H A D | nv50_pm.c | 180 int N1, N2, M1, M2; local
188 N2 = (coef & 0xff000000) >> 24;
196 clk = clk * N2 / M2;
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| H A D | nouveau_drv.h | 611 uint8_t N1, M1, N2, M2; member in struct:nouveau_pll_vals::__anon577::__anon578
613 uint8_t M1, N1, M2, N2;
1540 int *N1, int *M1, int *N2, int *M2, int *P);
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| H A D | nv04_crtc.c | 148 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
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| /drivers/net/wan/ |
| H A D | Kconfig | 250 config N2
251 tristate "SDL RISCom/N2 support"
254 Driver for RISCom/N2 single or dual channel ISA cards by
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| /drivers/tty/ |
| H A D | n_gsm.c | 73 #define N2 3 /* Retry 3 times */ macro
2163 gsm->n2 = N2;
2512 /* This will timeout if the link is down due to N2 expiring */
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| /drivers/net/wireless/brcm80211/brcmsmac/phy/ |
| H A D | phy_lcn.c | 2024 u16 N1, N2, N3, N4, N5, N6, N; local
2027 N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12))
2037 N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
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